# HW5 - Test The VGA Output Without A Monitor

###### tags: `DigitalDesign` `DD2` `ECE4514` `VESA` `VGA`

[TOC]

## VGA Monitor Alternatives

To test designs involve in video outputs, we usually need a monitor. However, VGA, on which we focus in HW5 & HW6, is not widely supported anymore. An VGA-to-HDMI adapter can be an alternative solution, to extend the HDMI monitors into adequate VGA testing equipments.

For some students, it is still too hard to find even a monitor. Or they have limited support due to the delay of delivery or local quarantine policy. We developed a program, or technically, a testbench, in order to help students who have limited access to proper hardwares.

## Test Your Design in ModelSim
### What Does the Testbench Do?
Once you instantiate your module in the testbench properly, it automatically runs the following functions:

1. Scans the VGA output frame by frame based on synchronization signals;
2. Stores each pixel in three frame buffer arrays;
3. Saves the screen buffer as a BMP picture.

To sum up, it prints out the screen for you and stores it as BMP files, so you can easily check what it could display on a real screen.

## How Do I Use the Testbench?
### Step1) Download it From Github
First, downlowd the files here: https://github.com/vt-ece4514-s20/VGA-Scanner

You can either use `git clone` or simply download it from the website. Then you must put each file into the right folder in your repository.

- XGA_tb: homework-5-yourid/colors
- XGA_testpatter_tb.v: homework-5-yourid/testpattern

### Step 2) Let The Testbench Generate VGA_CLK For You
In the original homework write-up, we ask you to add an PLL to generate the VGA clock @75MHz. Testing with the PLL is not impossible, but we have to perform the **post-simulation** or **gate-level simulation**, that is, we need to get our design compiled first, then simulate it with all the low-level components elaberated. You can imagine it will not be too fast, especially when you want to scan the entire 1024 * 768 screen.

In the testbench, we generate a 75MHz frequency for you. When instantiating, please add one input port to your top-level module. You may also need to wire it up with the origianl 75MHz signal in your design.

Previous:

   module XGA(
      input  wire       CLOCK_50,
      input  wire [3:0] KEY,
      input  wire [9:0] SW,
      output wire [7:0] VGA_R,
      output wire [7:0] VGA_G,
      output wire [7:0] VGA_B,
      ...

Insert one input port:

   module XGA(
      input  wire       CLOCK_50,
      input  wire       CLOCK_75, // <-- Wire this to your original 75MHz signal
      input  wire [3:0] KEY,
      input  wire [9:0] SW,
      output wire [7:0] VGA_R,
      output wire [7:0] VGA_G,
      output wire [7:0] VGA_B,
      ...

### Step 3) Remove Intel_PLL
In my own testrun, I did this:

   wire sys_clock;
   /*
   clockgen myclockgen(
      CLOCK_50, 
      rst, 
      sys_clock, 
      locked);
   */
   assign sys_clock = CLOCK_75;

### Step 4) Compile: vlib, vlog, & vsim
The rest of the process it very similar to what we had. But this time, the testbench is written partly with SystemVerilog syntax, we need to add `-sv` after `vlog` when compiling. Follow the steps below:

   vdel -lib work -all
   vlib work
   vlog -sv *.v
   vsim -c XGA_tb -L work -do "run -a; exit;"

`vdel` will clean out the library in case you had attemps with PLLs. You may have to modify the `vlog` command to make sure all your design files are compiled.

### Step 5) Sit Back and Let it Run
Scanning the whole screen may take a while for ModelSim. The actual running time for each person depends on the complexity of your design and your CPU. I managed to run it within few minutes on my laptop.

After the simulation is done, go check out your directory and open the pictures with any picture viewer to examine the screen output. Some example outputs are included in the Github repo: https://github.com/vt-ece4514-s20/VGA-Scanner/tree/master/example-outputs

## What To Turn In After The Simulation?
Since we will test run your submission with a real monitor, we need you to **add the PLL back** and **remove the CLOCK_75** input port in the top-level module. And please make sure your design is **compilable in Quartus Prime**. In principal, the "what to turn in" section in previous write-up remains unchanged.

## How the Testbench Works?
I had a plan to make some comment on this part too, but apparently making it available for you guys earlier is more important. Feel free to take a look at the code and let me know if you are truly interested in circuit verification.

## Conclusion
I always leave the conclusion section in my post. You got what you need above already!

Best,
Victor
03/31/2020