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    ###### tags: `數位系統設計` :::info [回共筆首頁](https://hackmd.io/zrsmsRtEQ-OrnGslDxT0NQ) [回科目首頁](https://hackmd.io/vXoSKbhKRV2nufoPIyxgyQ) ::: [上課投影片](https://moodle2.ntust.edu.tw/pluginfile.php/237204/mod_resource/content/1/L05_mem.pdf) [TOC] # Lecture05: Memory and Programmable Logic ## Introduction - Memory - Information storage - A collection of cells store binary information - RAM – Random-Access Memory - Read operation - Write operation - ROM – Read-Only Memory - Read operation only - A programmable logic device - ROM顧名思義,就是只能「讀」,但是SSD是一種ROM,但也能夠「寫入」,只是是有限的 ## Programmable Logic Device - Programmable Logic Device (PLD) ![](https://i.imgur.com/vVH5PBK.png) - (a) Conventional symbol 輸入腳都必須要接0 or 1,不然會燒掉。 - (b) Array logic symbol 就不需要每隻腳都接到。 ## Random-Access Memory ![](https://i.imgur.com/7I8JQhB.png =70%x) :::info 描述記憶體的大小:他有幾個words,一個word可以有幾個bits EX: $2^{k}$ 個words,要能夠挑到每個words,需要k個address lines,我可以寫入n個bit,讀取也是讀n個bit ::: ## 1024 x 16 Memory :::info 有1024個words,每個word有16個bit。 因為有1024個words指定,所以會用10個bit來控制 => Decoder ::: ![](https://i.imgur.com/A669Nsd.png =70%x) ## Write and Read Operations - Write operation - apply address - apply data - write - Read operation - apply address - read :::success 主要會用到 Enable 腳,控制Memory的工作及休息。由CPU來控制。 ::: ## Timing Waveforms - Access time - the time required to select a word and **read** it - Cycle time - the time required to complete a **write** operation :::info CPU 的 Cycle Time < Memory 的 Cycle Time 意思是 CPU 非常非常的快 ::: ![](https://i.imgur.com/YQYD05x.png =70%x) - CLOCK 是 CPU 的外頻 - 在寫入資料時,Memory Address, enable, input data 都要保持 ON - 讀取資料也類似 ![](https://i.imgur.com/cPVHq1m.png =70%x) ## Types of Memories - 1 - Random-access memory – RAM - Access time is the same regardless the data location - Cp.: hard disk, CD-ROM, DVD-ROM, tape (sequential access) - Static memory – SRAM - Information is stored in latches - Remains valid as long as power is applied - Short read/write cycle - Dynamic memory – DRAM - Information are stored in the form of charges on capacitors - The stored charge tends to discharge with time - Need to be refreshed (read and write back) every 64 ms – 256 ms - Reduced power consumption - Larger memory capacity :::warning - Random-access memory – RAM - 特點是你在**存取**每一個 location 的資料,他花費的 Access Time 幾乎是一樣的。 - Static memory – SRAM - 意思是你不需要額外去動用裡面的資料,他的值都在裡面 - Dynamic memory – DRAM - 資料儲存在裡面,一段時間後,必須要對資料**Refreshed** ::: :::danger DRAM 比 SRAM 省電,因為 SRAM無時無刻都在消耗電,因為會**漏電**,反而 DRAM 只有在要 Refreshed 的時候,才會消耗。 ::: ## DRAM ![](https://i.imgur.com/eSSYRFw.png =50%x) - Word Line 控制是要Read/Write - Bit Line 是傳入或是讀取 Data - Capacitor 電容來儲存資料 ## SRAM ![](https://i.imgur.com/OpDrvnj.png =50%x) - WL - Word Line 控制是要Read/Write - BL - Bit Line 是傳入或是讀取 Data - 中間兩個 Not Gate 共四個電晶體,組合成 Latch 來儲存資料 :::info 可以發現,SRAM 在 Read 資料時,資料還是會留在 Latch 裡面,不會消失,但是 DRAM 在 Read 資料時,電容會放電,資料就會不見。 所以 DRAM 存取玩資料後,還要把資料更新回去。 ::: ## Types of Memories - 2 - Volatile - Lose stored information when power is turned off - SRAM, DRAM - Non-volatile - Retains its stored information after the removal of power - ROM - EPROM, EEPROM - Flash memory ![](https://i.imgur.com/4WCW6rP.png =70%x) ## Internal Construction ![](https://i.imgur.com/2eqceRZ.png) - 1 維的 array ## Coincident Decoding - two-dimensional selection scheme - reduce the complexity of the decoding circuits - 舉例有1024個資料 -> 10 個 bits - 1 維 => 1024 AND10 => AND Gate 有 10 個 input - 2 維 => (32 AND5)*2 => 兩個 5 input 的 AND Gate ![](https://i.imgur.com/0p9lnbb.png) - 先對 row decode,再對 column decode - 缺點:要一筆資料時,必須要先拿32筆資料,再取其中的一筆,是我們想要的 :::warning Q. 為什麼不做3維、4維...? A. 實務上有辦法做出來,但因為還沒有想出多維的好處,那就不需要花成本研發這種想法。 ::: ## Address Multiplexing - To reduce the number of pins in the IC package - consider a 64Kx1 DRAM - 16-bit address lines - Multiplex the address lines in one set of address input pins - RAS: 8-bit row address strobe - CAS: 8-bit column address strobe ## Basic DRAM Chip Organization ![](https://i.imgur.com/tJM1rYe.png) ## DRAM Sub-system Hierarchy ![](https://i.imgur.com/vQ9zCmq.jpg) - chip 就是每一個晶片顆粒 - 每顆 chip 會有好幾個 bank - rank 就是幾個 chip 組成一個 rank - 通常運作的時候,都是一個 rank 在工作 :::info address MUX: 舉例:雙通道記憶體4GB的資料可以處理,並不會讓第一個通道負責0~2GB,另一個通道負責2GB~4GB,因為可能平常的資料只會用到0~1GB的位址,這樣就只會有一個通道一直在運作,所以會用 address MUX,讓位址可以在雙通道多一點變化,達到雙通道的效能。 ::: ## Read Only Memory - Store permanent binary information - $2^{k}$ x n ROM - k address input lines - Enable input(s) - Three-state outputs ![](https://i.imgur.com/SklkODI.png) - 舉例:3 bit 做出平方數 ![](https://i.imgur.com/voRR24x.png) ## Combinational PLDs ![](https://i.imgur.com/8E2z4M0.png) ## PLA - PLA Implementation ![](https://i.imgur.com/oDRnx6S.png) ## Sequential Programmable Devices - 可以用 PLA 實現 Combinational Circuits - 若要實現 Sequential Circuits,還是需要 Flip-Flop ![](https://i.imgur.com/PViiMPa.png) ### Complex PLD - Put a lot of PLDS on a chip - Add wires between them whose connections can be programmed - Use fuse/EEPROM technology ![](https://i.imgur.com/6lCFK6z.png) :::info CPLD已經過時了,現在比較主流的是FPGA ::: ### FPGA (Field-Programmable Gate Arrays) ![](https://i.imgur.com/hqu3KTs.png) - 最左邊的就是 16 個 truth table - ABCD 為四個 input ![](https://i.imgur.com/3Zse7bN.png) - 只需要17個bit 就可以實現Combination circuits 或是 Sequential circuits - Interconnect Resorce 讓資料在內部傳遞的元件,可以決定要不要傳遞 ![](https://i.imgur.com/Ms5eDxF.png) - Switch Matrix 讓資料可以轉彎 ![](https://i.imgur.com/CwhOjGv.png)

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