## Getting Started
<details>
<summary>
Getting Started
</summary>
```verilog=
module top_module( output one );
//Victor_huang1123
assign one = 1'b1;
endmodule
```
</details>
<details>
<summary>
Output Zero
</summary>
```verilog=
module top_module(
output zero
);// Module body starts after semicolon
endmodule
```
</details>
## Verilog Language
<details>
<summary>
Basics
</summary>
<details>
<summary>
Simple wire
</summary>
```verilog=
module top_module( input in, output out );
assign out=in;
endmodule
```
</details>
<details>
<summary>
Four wires
</summary>
```verilog=
module top_module(
input a,b,c,
output w,x,y,z );
assign w=a;
assign x=b;
assign y=b;
assign z=c;
endmodule
```
</details>
<details>
<summary>
Inverter
</summary>
```verilog=
module top_module( input in, output out );
assign out = !in;
endmodule
```
</details>
<details>
<summary>
AND gate
</summary>
```verilog=
module top_module(
input a,
input b,
output out );
assign out =a& b;endmodule
```
</details>
<details>
<summary>
NOR gate
</summary>
```verilog=
module top_module(
input a,
input b,
output out
);
assign out = ~(a|b);
endmodule
```
</details>
<details>
<summary>
XNOR gate
</summary>
```verilog=
module top_module(
input a,
input b,
output out );
assign out=~(a^b);
endmodule
```
</details>
<details>
<summary>
Declaring wires
</summary>
```verilog=
module top_module(
input a,
input b,
input c,
input d,
output out,
output out_n );
wire x,y;
assign x=a& b;
assign y=c& d;
assign out=x|y;
assign out_n=~(x|y);
endmodule
```
</details>
<details>
<summary>
7458 chip
</summary>
```verilog=
module top_module (
input p1a, p1b, p1c, p1d, p1e, p1f,
output p1y,
input p2a, p2b, p2c, p2d,
output p2y );
wire p2ab,p2cd,p1abc,p1def;
assign p2ab=p2a& p2b;
assign p2cd=p2c& p2d;
assign p2y=p2ab|p2cd;
assign p1abc=p1a&p1b& p1c;
assign p1def=p1d&p1e& p1f;
assign p1y=p1abc|p1def;
endmodule
```
</details>
</details>
<details>
<summary>
Vectors
</summary>
<details>
<summary>
Vectors
</summary>
```verilog=
module top_module (
input wire [2:0] vec,
output wire [2:0] outv,
output wire o2,
output wire o1,
output wire o0
);
assign o2 = vec[2];
assign o1 = vec[1];
assign o0 = vec[0];
assign outv = vec[2:0];
endmodule
```
</details>
<details>
<summary>
Vectors in more detail
</summary>
```verilog=
`default_nettype none // Disable implicit nets. Reduces some types of bugs.
module top_module(
input wire [15:0] in,
output wire [7:0] out_hi,
output wire [7:0] out_lo );
assign out_hi=in[15:8];
assign out_lo=in[7:0];
endmodule
```
</details>
<details>
<summary>
Vector part select
</summary>
```verilog=
module top_module(
input [31:0] in,
output [31:0] out );//
// assign out[31:24] = ...;
assign out[31:24]=in[7:0];
assign out[23:16]=in[15:8];
assign out[15:8]=in[23:16];
assign out[7:0]=in[31:24];
endmodule
```
</details>
<details>
<summary>
Bitwise operators
</summary>
```verilog=
module top_module(
input [2:0] a,
input [2:0] b,
output [2:0] out_or_bitwise,
output out_or_logical,
output [5:0] out_not
);
assign out_or_bitwise=a|b;
assign out_or_logical=a||b;
assign out_not[5:3]=~b;
assign out_not[2:0]=~a;
endmodule
```
</details>
<details>
<summary>
Four-input gates
</summary>
```verilog=
module top_module(
input [3:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and=in[3]&in[2]&in[1]&in[0];
assign out_or=in[3]|in[2]|in[1]|in[0];
assign out_xor=in[3]^in[2]^in[1]^in[0];
endmodule
```
</details>
<details>
<summary>
Vector concatenation operator
</summary>
```verilog=
module top_module (
input [4:0] a, b, c, d, e, f,
output [7:0] w, x, y, z );//
// assign { ... } = { ... };
assign {w,x,y,z}={a,b,c,d,e,f,2'b11};
endmodule
```
</details>
<details>
<summary>
Vector reversal 1
</summary>
```verilog=
module top_module(
input [7:0] in,
output [7:0] out
);
assign out={in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7]};
endmodule
```
</details>
<details>
<summary>
Replication operator
</summary>
```verilog=
module top_module (
input [7:0] in,
output [31:0] out
);
// Sign-extend the 8-bit input to 32 bits
assign out = { {24{in[7]}}, in };
endmodule
```
</details>
<details>
<summary>
More replication
</summary>
```verilog=
module top_module (
input a, b, c, d, e,
output [24:0] out );//
// The output is XNOR of two vectors created by
// concatenating and replicating the five inputs.
// assign out = ~{ ... } ^ { ... };
assign out=~{{5{a}},{5{b}},{5{c}},{5{d}},{5{e}}}^{{5{a,b,c,d,e}}};
endmodule
```
</details>
</details>
<details>
<summary>
Modules Hierarchy
</summary>
<details>
<summary>
Modules
</summary>
```verilog=
module top_module ( input a, input b, output out );
mod_a(a,b,out);
endmodule
```
</details>
<details>
<summary>
Connecting ports by position
</summary>
```verilog=
module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
mod_a(out1,out2,a,b,c,d);
endmodule
```
</details>
<details>
<summary>
Connecting ports by name
</summary>
```verilog=
module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
mod_a(.out1(out1),.out2(out2),.in1(a),.in2(b),.in3(c),.in4(d));
endmodule
```
</details>
<details>
<summary>
Three modules
</summary>
```verilog=
module top_module (
input clk,
input d,
output q
);
wire a, b; // Create two wires. I called them a and b.
// Create three instances of my_dff, with three different instance names (d1, d2, and d3).
// Connect ports by position: ( input clk, input d, output q)
my_dff( clk, d, a );
my_dff( clk, a, b );
my_dff( clk, b, q );
endmodule
```
</details>
<details>
<summary>
Modules and vectors
</summary>
```verilog=
module top_module (
input clk,
input [7:0] d,
input [1:0] sel,
output reg [7:0] q
);
wire [7:0] q1, q2, q3;
my_dff8(clk, d, q1);
my_dff8(clk, q1, q2);
my_dff8(clk, q2, q3);
always @(*) begin
case (sel)
2'b00: q = d;
2'b01: q = q1;
2'b10: q = q2;
2'b11: q = q3;
//default: q = 8'b00000000; // Optional default case
endcase
end
endmodule
```
</details>
<details>
<summary>
Adder 1
</summary>
```verilog=
module top_module(
input [31:0] a,
input [31:0] b,
output [31:0] sum
);
//module add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );
wire c,x;
add16 add1(a[15:0],b[15:0],1'b0,sum[15:0],c);
add16 add2(a[31:16],b[31:16],c,sum[31:16],x);
endmodule
```
</details>
<details>
<summary>
Adder 2
</summary>
```verilog=
module top_module (
input [31:0] a,
input [31:0] b,
output [31:0] sum
);//module add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );
wire c,x;
add16 add1(a[15:0],b[15:0],1'b0,sum[15:0],c);
add16 add2(a[31:16],b[31:16],c,sum[31:16],x);
endmodule
module add1 ( input a, input b, input cin, output sum, output cout );
assign sum=a^b^cin;
assign cout=(a&b)|(cin&(a^b));
// Full adder module here
endmodule
```
</details>
<details>
<summary>
Carry-select adder
</summary>
```verilog=
module top_module (
input [31:0] a,
input [31:0] b,
output [31:0] sum
);
wire [15:0] reg1, reg2;
wire c, c1, c2;
// Instantiate add16 modules
add16 add1 (a[15:0], b[15:0], 1'b0, sum[15:0], c);
add16 add2 (a[31:16], b[31:16], 1'b0, reg1, c1);
add16 add3 (a[31:16], b[31:16], 1'b1, reg2, c2);
// Assign upper 16 bits of sum based on carry flags
always @* begin
case(c)
1'b0: sum[31:16] = reg1;
1'b1: sum[31:16] = reg2;
endcase
end
endmodule
```
</details>
<details>
<summary>
Adder-subtractor
</summary>
```verilog=
module top_module(
input [31:0] a,
input [31:0] b,
input sub,
output [31:0] sum
);
wire c,cout;
add16 add1(a[15:0],b[15:0]^{16{sub}},sub,sum[15:0],c);
add16 add2(a[31:16],b[31:16]^{16{sub}},c,sum[31:16],cout);
endmodule
```
</details>
</details>
<details>
<summary> Procedures </summary>
<details>
<summary>
Always blocks(combinational)
</summary>
```verilog=
// synthesis verilog_input_version verilog_2001
module top_module(
input a,
input b,
output wire out_assign,
output reg out_alwaysblock
);
assign out_assign = a & b;
always @(*) out_alwaysblock = a & b ;
endmodule
```
</details>
<details>
<summary>
Always blocks(clocked)
</summary>
```verilog=
// synthesis verilog_input_version verilog_2001
module top_module(
input clk,
input a,
input b,
output wire out_assign,
output reg out_always_comb,
output reg out_always_ff );
assign out_assign=a^b;
always@(*) out_always_comb = a^b;
always@(posedge clk)out_always_ff =a^b;
endmodule
```
</details>
<details>
<summary>
If statement
</summary>
```verilog=
// synthesis verilog_input_version verilog_2001
module top_module(
input a,
input b,
input sel_b1,
input sel_b2,
output wire out_assign,
output reg out_always );
assign out_assign = (sel_b1&&sel_b2)?b:a;
always@(*) out_always =(sel_b1&&sel_b2)?b:a;
endmodule
```
</details>
<details>
<summary>
If statement latches
</summary>
```verilog=
// synthesis verilog_input_version verilog_2001
module top_module (
input cpu_overheated,
output reg shut_off_computer,
input arrived,
input gas_tank_empty,
output reg keep_driving ); //
always @(*) begin
if (cpu_overheated)
shut_off_computer = 1;
else
shut_off_computer=0;
end
always @(*) begin
if (~arrived)
keep_driving = ~gas_tank_empty;
else keep_driving=0;
end
endmodule
```
</details>
<details>
<summary>
Case statement
</summary>
```verilog=
// synthesis verilog_input_version verilog_2001
module top_module (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3:0] data5,
output reg [3:0] out );//
always@(*) begin // This is a combinational circuit
case(sel)
3'b000:out=data0;
3'b001:out=data1;
3'b010:out=data2;
3'b011:out=data3;
3'b100:out=data4;
3'b101:out=data5;
default: out=3'b000;
endcase
end
endmodule
```
</details>
<details>
<summary>
Priority encoder
</summary>
```verilog=
// synthesis verilog_input_version verilog_2001
module top_module (
input [3:0] in,
output reg [1:0] pos );
always@(*)
casez(in)
4'b???1:pos=2'b00;
4'b??10:pos=2'b01;
4'b?100:pos=2'b10;
4'b1000:pos=2'b11;
default: pos = 2'b00; // No input is high
endcase
endmodule
```
</details>
<details>
<summary>
Avoiding latches
</summary>
```verilog=
// synthesis verilog_input_version verilog_2001
module top_module (
input [15:0] scancode,
output reg left,
output reg down,
output reg right,
output reg up
);
always @(*) begin
// Initialize outputs
left = 1'b0;
down = 1'b0;
right = 1'b0;
up = 1'b0;
// Case statement to assign outputs based on scancode
case (scancode)
16'he06b: left = 1'b1; // Left arrow
16'he072: down = 1'b1; // Down arrow
16'he074: right = 1'b1; // Right arrow
16'he075: up = 1'b1; // Up arrow
endcase
end
endmodule
```
</details>
</details>
<details>
<summary>
More Verilog Features
</summary>
<details>
<summary>
Conditional tenary operator
</summary>
```verilog=
module top_module(
input [7:0] a, b, c, d,
output [7:0] min);//
// assign intermediate_result1 = compare? true: false;
reg[1:0]reg1;
assign reg1[0] = (a < b) ? 1'b1 : 1'b0;
assign reg1[1] = (c < d) ?1'b1:1'b0;
always@(*)
case(reg1)
2'b00:min=(b<d)?b:d;
2'b01:min=(a<d)?a:d;
2'b10:min=(c<b)?c:b;
2'b11:min=(a<c)?a:c;
endcase
endmodule
```
</details>
<details>
<summary>
Reduction operators
</summary>
```verilog=
module top_module (
input [7:0] in,
output parity);
assign parity = ^in;
endmodule
```
</details>
<details>
<summary>
Reduction:Even wider gates
</summary>
```verilog=
module top_module(
input [99:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and=& in;
assign out_or=|in;
assign out_xor=^in;
endmodule
```
</details>
<details>
<summary>
Combinational for-loop:Vector reversal 2
</summary>
```verilog=
module top_module(
input [99:0] in,
output [99:0] out
);
genvar i;
generate
for (i = 0; i < 100; i = i + 1) begin:revese
assign out[i] = in[99 - i];
end
endgenerate
endmodule
```
</details>
<details>
<summary>
Combinational for-loop:255-bit population count
</summary>
```
module top_module (
input [254:0] in,
output reg [7:0] out
);
always @* begin
reg [7:0] reg1;
reg1 = 0;
for (int i = 0; i < 255; i = i + 1) begin
reg1 = (in[i] == 1) ? reg1 + 1 : reg1;
end
out = reg1;
end
endmodule
```
</details>
<details>
<summary>
Generate for-loop: 100-bit binary adder 2
</summary>
```verilog=
module top_module(
input [99:0] a, b,
input cin,
output [99:0] cout,
output [99:0] sum );
always@(*)begin
for(int i=0;i<100;i++)begin
if(i==0)begin
cout[i]=a[i]&b[i]|a[i]&cin|b[i]&cin;
sum[i]=a[i]^b[i]^cin;
end
else begin
cout[i]=a[i]&b[i]|a[i]&cout[i-1]|b[i]&cout[i-1];
sum[i]=a[i]^b[i]^cout[i-1];
end
end
end
endmodule
```
</details>
<details>
<summary>
Generate for-loop: 100-digit BCD adder
</summary>
```verilog=
module top_module(
input [399:0] a, b,
input cin,
output cout,
output [399:0] sum );
reg[99:0]reg1;
generate
genvar i;
for(i=0;i<400;i=i+4)begin:bcd
if(i==0)bcd_fadd bf(a[i+3:i],b[i+3:i],cin,reg1[0],sum[i+3:i]);
else bcd_fadd bf(a[i+3:i],b[i+3:i],reg1[i/4-1],reg1[i/4],sum[i+3:i]);
end
endgenerate
assign cout=reg1[99];
endmodule
```
</details>
</details>
### Circuits
<details>
<summary>
Combinational Logic
</summary>
<details>
<summary>
Basic Gates
</summary>
<details>
<summary>
Wire
</summary>
```verilog=
module top_module (
input in,
output out);
assign out=in;
endmodule
```
</details>
<details>
<summary>
GND
</summary>
```verilog=
module top_module (
output out);
assign out=1'b0;
endmodule
```
</details>
<details>
<summary>
</summary>
```verilog=
```
</details>
<details>
<summary>
</summary>
```verilog=
```
</details>
</details>
</details>
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