# Hazar
[TOC]
## Structural hazards(Source hazard):
:::danger
- **CPI:**
- **1.23+0.1(N–5)~N=stage-per-pip~**

- **Time cycle per ins**:

- **T~c~=(740/N+90)~N=stage-per-pip~**

:::
:::success
**HW** cannot support this **combination of instructions**
:::info
(**single** person to fold and put clothes away)

**<font color = 'red'>不同指令同時對某硬體做存取</font>**
:::
## Data hazards:
:::success
Instruction depends on result of prior instruction<font color = "red"> **still in the pipeline (missing sock)</font>
當管道因為某一步驟必須等待其他步驟而停滯，起因於兩道指令俱有<font color = "red">*相依性*</font>** also call it **data dependency**

:::

:::info
### 1. Read after write (RAW)
**(i2 tries to read a source before i1 writes to it)** A read after write (RAW) data hazard refers to a situation where an instruction refers to a result that has not yet been calculated or retrieved. This can occur because even though an instruction is executed after a prior instruction, the prior instruction has been processed only partly through the pipeline.

:::warning

**Example**


The first instruction is calculating a value to be saved in register R2, and the second is going to use this value to compute a result for register R4. However, in a pipeline, when operands are fetched for the 2nd operation, the results from the first have not yet been saved, and hence a data dependency occurs.

A data dependency occurs with instruction i2, as it is dependent on the completion of instruction i1.
:::

:::info
### 2. Write after read (WAR)
(i2 tries to write a destination before it is read by i1) A write after read (WAR) data hazard represents a problem with concurrent execution.
:::warning

Example
For example:

In any situation with a chance that i2 may finish before i1 (i.e., with concurrent execution), it must be ensured that the result of register R5 is not stored before i1 has had a chance to fetch the operands.
:::
:::info
### 3. Write after write (WAW)
(i2 tries to write an operand before it is written by i1) A write after write (WAW) data hazard may occur in a concurrent execution environment.
:::warning
Example
For example:

The write back (WB) of i2 must be delayed until i1 finishes executing.
:::
:::danger

### 解決方案:
1. 加入low cost to implement
2. reduces **[IPC](https://en.wikipedia.org/wiki/Instructions_per_cycle)**
3. Minimizing RAW stalls
4. 可使用forwarding解決
5. load-use data hazard，即使使用forwarding還是要stall一個cycle
6. code scheduling 可避免hazard
:::

## Control hazards (branch hazards):
:::success
Caused by delay between the fetching of instructions and decisions about changes in control flow (**branches** and **jumps**).
:::

:::info
**Hazar會發生**

1. Branch jump to new MEM location
2. invalidating all prior stages in the pipeline(之前所有的`PIP`指令都不見了)
:::

:::danger
### **避免 control** hazards microarchitectures can:

- insert a pipeline **bubble[^comparison]** , guaranteed to increase **latency**
- Branch Prediction：先做錯了再換
:::warning
1. Not Taken
2. Static Branch Prediction：根據跳躍類型預測，例如loop猜會往回跳，if猜往前跳
3. Dynamic Branch Prediction：會考量每一個分支指令的特性，程式運作過程中會改變對一道分支的預測，假設之後的Branch會照著「趨勢」走。
(**OPT ALGO**)
:::

:::info
- 但是使用這些解決方案都會造成能源的浪費
- 效能下降(因為要回復這些錯誤的訊息)
:::
## 補充:
### [Bubbling](https://en.wikipedia.org/wiki/Pipeline_stall)
:::warning

- Bubbling in the pipeline, <font color ="red">可稱為 a **pipeline break** or **pipeline stall**</font>, is a method to <font color ="red">包含 **data**, **structural**, and **branch** hazards</font>. As instructions are fetched, control logic determines whether a hazard could/will occur.
:::
:::info
If this is true, then the control logic inserts no operations (**NOPs**) into the pipeline. Thus, before the next instruction (which would 發生 `hazard`)
:::
### 結語
:::success

executes, the prior one will have had sufficient time to finish and prevent the hazard. If the number of NOPs equals the number of stages in the pipeline, the processor has been cleared of all instructions and can proceed free from hazards. All forms of stalling introduce a delay before the processor can resume execution.
:::
:::
:::info
補充
Which of the following statement **is correct**?
(a) Pipelining improves the performance of a processor by <font color="red">decreasing the latency</font> of a job
(e.g., an instruction) to be done.
(b) The more balanced pipeline stages a specific datapath has, the higher performance this
pipelined datapath can achieve.
(c) Every single instruction, when being executed in a <font color ="red"> n-stage</font> pipelined datapath, consistently. **single ins 都是在單一stage完成**
needs n clock cycles before its execution is completely done.

(d) It is likely to have fewer hazards and less severe impact of hazards(STR) with deeper design of pipelining (i.e., more pipeline stage).**more pip more hazard 產生**

(e) The number of pipeline stages monotonically [deep pip](https://www.sciencedirect.com/topics/computer-science/pipeline-stage)
:::spoiler
Answer: (b)
註:正在n-stage pipelinedatapath中被執行的單一指令,在完成執行前所需的clock個數小於n
:::
[^comparison]: [Bubbling](https://en.wikipedia.org/wiki/Pipeline_stall)