# AS4 Part2 Verilog Practice

[TOC]

## Design Flow

## Tutorial

{%speakerdeck dppa1008/useful-tools-for-hardware-design %}

## Commands

### Login to a server

- Mac

1. Download [Xquartz](https://www.xquartz.org/)

2. Login:

    ssh -X [e-mail]

- Login a server node

ssh -X ic23

### Run the code

- Use makefile

make q1 # = ncverilog q1_tb.v q1.v +access+r
make q2
make q3

### nWave

nwave

## Questions

### Question 1 Design a Testbench

Please design a testbench to verify the following code and explain your testbench in your report.

module func (A, B, S, E, Q);
  input [1:0] A, B;
  input S, E;
  output[1:0] Q;
  
  assign Q = E ? (S ? A : B) : 'bz;
  
endmodule

<font color=gray>You can find the template on ILMS.</font>

---

### Question 2 ALU

Please implement an [ALU( arithmetic-logic unit)](https://en.wikipedia.org/wiki/Arithmetic_logic_unit) and explain your design in the report. You should design a testbench to verify the code by yourselves.

The following table lists the functions of ALU you have to implement in this question.

| `sel` (selector) | Operation | Description |
| ---------------- | --------------- | ----------------------------------------------- |
| 000 | Y = `32'b0` | |
| 001 | Y = A & B | Bitwise AND |
| 010 | Y = A \| B | Bitwise OR |
| 011 | Y = A ^ B | Bitwise exclusive OR |
| 100 | Y = `not` A | Bitwise complement |
| 101 | Y = A - B | Subtract |
| 110 | Y = A + B | Add (assume A and B are 2’s complement numbers) |
| 111 | Y = A << `1'b1` | Shifting |

You should also implement the following detecting signals in your design.

| Signal | Description |
| ------ | ------------------------------------- |
| `Zero` | `Zero = 1`, if Y is zero. `0` otherwise. |
| `Negative` | `Negative = 1`, if Y is negative. |

#### Input

> `A`: 32-bit 2’s complement number.
> `B`: 32-bit 2’s complement number.
> `sel`: 3-bit selector

#### Output

> `Y`: 32-bit 2’s complement number
> `Zero`: zero detector
> `Negative`: negative detector

module ALU (A, B, sel, Y, Negative, Zero);
  input [32 - 1:0] A, B;
  output[32 - 1:0] Y;
  input sel;
  output Negative, Zero;
  
  // your design
  
endmodule

<font color=gray>You can find the template on ILMS.</font>

#### Hints
<font color=gray>Use `case` statement.</font>
<font color=gray>Read the [tutorials](https://hackmd.io/@dppa1008/Logic_Design_Mak) before starting the lab.</font>
<font color=gray>Remembet that A, B and Y are <font color=#bf2222>2'complement</font> numbers.</font>

---

### Q3 D-Flip Flop

Please design a **latch** module (fig. 1) and implement a clk <font color=#bf2222> positive</font> edge trigger flip-flop (fig. 2).

After you finish Q3, please take a screenshot of the waveform.

<font color=gray>p.s. You don't need to design the testbench for this question (tb is on ILMS). </font> <font color=#bf2222>**But you have to debug this question by checking the waveform.**</font>

<img src="https://i.imgur.com/fG7YXID.jpg" style="zoom: 45%; display: block; margin: auto;" />

<font color=white>..</font>

module Flip_Flop (clk, d, q);
	input clk;
	input d;
	output q;
  Latch Master ( .clk (), .d (), .q () );
  Latch Slave  ( .clk (), .d (), .q () );
endmodule

module Latch (clk, d, q);
	input clk;
	input d;
	output q;
	
  // our design
 
endmodule

<font color=gray>You can find the template on ILMS.</font>

---

## Tools
### Testbench
The idea of testbench is using a computer simulator to test your circuit.

- [Tutorial](https://hackmd.io/@dppa1008/testbench)
- [Dive deeper](https://verilogguide.readthedocs.io/en/latest/verilog/testbench.html)

{%speakerdeck dppa1008/testbench %}

### Makefile
A makefile is a file (by default named "Makefile") containing a set of directives used by a make build automation tool to generate a target/goal. [wiki](https://en.wikipedia.org/wiki/Makefile)

- [Tutorial](https://hackmd.io/@dppa1008/)
- [Dive deeper](https://hackmd.io/@sysprog/SySTMXPvl?type=view)

{%speakerdeck dppa1008/simple-makefile %}

:::danger
You don't need to implement a makefile in this lab.
:::

### nWave

nWave is one of the best waveform (`*.vcd` or `*.fsdb`) viewers. We can debug easily by checking the waveform file dumped during simulation. See [here](https://hackmd.io/@dppa1008/nWave) for more infomations.

{%speakerdeck dppa1008/simple-nwave %}

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## Assignment Rules

1. Part2 Deadline: <font color=#bf2222>**5/11**</font> <font color=gray>(Deadline of part1 is 5/7)</font>

2. Submit your code to ILMS. Please upload the questions separately. <font color=#bf2222>**Do not** zip them</font>.

3. The file content tree should look like:
- q1.v
- q2.v
- q3.v
- q1_tb.v
- q2_tb.v
- q3_tb.v
- as4_StudentID<font color=#bf2222>**.pdf**</font> (ex. `lab1_105066666.pdf`)

**<font color=#bf2222>wrong filename = no point.</font>**
**<font color=#bf2222>wrong module name = no point.</font>**

4. Tell us how you design Q1 and Q2 in your report.
- Up to 4 pages
- 3 pages for implementation details
- 1 pages for screenshot of nWave

5. <font color=gray>(Optional) Suggestions on the course or lab.</font>

---