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# <center><i class="fa fa-edit"></i>NR_UE_sched_ctrl_t</center>
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[TOC]

typedef struct {
  /// the currently active BWP in DL
  NR_BWP_Downlink_t *active_bwp;
  /// the currently active BWP in UL
  NR_BWP_Uplink_t *active_ubwp;
  /// CCE index and aggregation, should be coherent with cce_list
  NR_SearchSpace_t *search_space;
  NR_ControlResourceSet_t *coreset;

  /// CCE index and Aggr. Level are shared for PUSCH/PDSCH allocation decisions
  /// corresponding to the sched_pusch/sched_pdsch structures below
  int cce_index;
  uint8_t aggregation_level;
  /// maximum aggregation level for UE, can be used to select level
  int maxL;
  /// PUCCH scheduling information. Array of two: HARQ+SR in the first field,
  /// CSI in second.  This order is important for nr_acknack_scheduling()!
  NR_sched_pucch_t sched_pucch[2];

  /// PUSCH semi-static configuration: is not cleared across TTIs
  NR_pusch_semi_static_t pusch_semi_static;
  /// Sched PDSCH: scheduling decisions, copied into HARQ and cleared every TTI
  NR_sched_pusch_t sched_pusch;

  /// uplink bytes that are currently scheduled
  int sched_ul_bytes;
  /// estimation of the UL buffer size
  int estimated_ul_buffer;

  /// PHR info: power headroom level (dB)
  int ph;
  /// PHR info: nominal UE transmit power levels (dBm)
  int pcmax;

  /// PDSCH semi-static configuration: is not cleared across TTIs
  NR_pdsch_semi_static_t pdsch_semi_static;
  /// Sched PDSCH: scheduling decisions, copied into HARQ and cleared every TTI
  NR_sched_pdsch_t sched_pdsch;
  /// For UL synchronization: store last UL scheduling grant
  frame_t last_ul_frame;
  sub_frame_t last_ul_slot;

  /// total amount of data awaiting for this UE
  uint32_t num_total_bytes;
  /// per-LC status data
  mac_rlc_status_resp_t rlc_status[MAX_NUM_LCID];

  /// Estimation of HARQ from BLER
  NR_DL_bler_stats_t dl_bler_stats;

  int lcid_mask;
  int lcid_to_schedule;
  uint16_t ta_frame;
  int16_t ta_update;
  bool ta_apply;
  uint8_t tpc0;
  uint8_t tpc1;
  int raw_rssi;
  int pusch_snrx10;
  int pucch_snrx10;
  uint16_t ul_rssi;
  uint8_t current_harq_pid;
  int pusch_consecutive_dtx_cnt;
  int pucch_consecutive_dtx_cnt;
  int ul_failure;
  struct CSI_Report CSI_report[MAX_CSI_REPORTS];
  bool SR;

  /// information about every HARQ process
  NR_UE_harq_t harq_processes[NR_MAX_NB_HARQ_PROCESSES];
  /// HARQ processes that are free
  NR_list_t available_dl_harq;
  /// HARQ processes that await feedback
  NR_list_t feedback_dl_harq;
  /// HARQ processes that await retransmission
  NR_list_t retrans_dl_harq;
  /// information about every UL HARQ process
  NR_UE_ul_harq_t ul_harq_processes[NR_MAX_NB_HARQ_PROCESSES];
  /// UL HARQ processes that are free
  NR_list_t available_ul_harq;
  /// UL HARQ processes that await feedback
  NR_list_t feedback_ul_harq;
  /// UL HARQ processes that await retransmission
  NR_list_t retrans_ul_harq;
  NR_UE_mac_ce_ctrl_t UE_mac_ce_ctrl;// MAC CE related information
} NR_UE_sched_ctrl_t;