# Lab 3 Report

Group members:
- Xuyang Zhou ([e-mail])
- Peicheng (Mike) Shi ([e-mail])
- Chang Xu ([e-mail])

## Introduction
Stop watch is a very useful in our daily life, and in this lab we aim to implement a stop watch on the Nexys3 board using FPGA. We also wanted to add a variety of features to improve the usability of the stop watch. We made our stop watch adjustable and resetable. It also have a debouncing feature to bring smoother experience to its users. We created and designed a set of modules and testbenches to achieve our goal, and the result was successful.

## Our Design

### `stopwatch` Module
The stopwatch module is the main control module of the entire project. It takes in input from the nexy3 board including RST(reset), ADJ(adjust), SEL(select), pause, It then calls the following modules using the initial input we have. The signals will be firstly pass to the increment module and generate the next minutes and seconds that should be displayed as output. Then, signals will be passed to the display module to be displayed one by one on the board in a rapid speed(differentiates when inputs are different). The adjust module results after the display module which disables display at a certain rate.

### `clock` Module
The clock module takes in the master clock (100M Hz) and outputs 4 clock signals with different frequencies:
- Blinking clock (4Hz) that controls the blinking frequency when adjusting the stopwatch.
- Watch clock (1Hz) that increment the second counter every second.
- Adjustment clock (2Hz) that increment the counters twice per second when adjusting the stopwatch.
- Display clock (250Hz) that controls the refresh rate of the 7-segment display.

### `debouncer` Module
The debouncer module takes in various clocks we created as needed. To ensure the valadity of the input signal. The function set the 2-bit buffer to be filled with one if a signal input is detected. Using an anti-stack-like insertion of 0 at every positive clock edge to a 2-bit buffer and output the last bit of the buffer to ensure that signals passed in is not a miss-press or noise.

### `increment` Module
The increment module is responsible for incrementing the digits every second and incrementing the digits quicker if adjust is selected.

We designed our module to take in the `ADJ, SEL, pause, reset` signals and `master_clk,watch_clk,adj_clk` clocks. The module will output the four numerical digits. If the `reset` signal is triggered, we set all digits back to `0`. Then, we increment the digits normally. Finally, the module outputs the incremented digits for the display module.

### `display` Module
This is the module that is responsible for displaying digits on the seven-digit display of the Nexys3 board.

Going through the user manual of the Nexys3 board, we learnt that `an3,an2,an1,an0` are used to represent the four digits whereas `ca,cb,cc,cd,ce,cf,cg,dp` are used to represnet different segments on each digit.

With that in mind, we designed our module to take in the four numerical digits as well as the display clock as input parameters. After that, for every (display) clock cycle, we draw a single display digit (i.e. draw `an0,an1,an2,an3` respectively in different cycles. Then, we used different cases to match numerical digits with combinations of segment codes. Finally, we will output the display location (`an0` to `an3`) as well as the display segments (`ca` to `dp`). These varaiables matches the `Nexys3.ucf` file to display the numbers on the seven-segment display.

### `adjust` Module
`adjust` module happens after `display`. It takes in the debounced SEL and ADJ signal, the blinking clock, and `an0`-`an3`, the signals controlling the display digit of the 7-segment display. Based on the combination of `SEL` and `ADJ` signals, this module overrides the signals of either `an0`+`an1` or `an2`+`an3` to be synchronized with the blinking clock. That is, when the blinking clock reaches the rising edge, we turn-off the display of the selected digits, and resume diplay when the next rising edge reached.

This way, the digits of minutes or seconds will be blacked out per blinking clock frequency, which simulates the "blinking" behavior when we adjust the stopwatch.

## Simulation
We did simulations on all sub-modules excepting `stopwatch` before integrating them together. During the process, example inputs in the lab documentation are taken as test cases for each module. Finally, after we finished the `stopwatch` module, a set of test cases covering edge cases are tested on our overall design.

During simulation, we found several difficulties with testing our code on the Nexys3 board as we are new to it. Sometimes we hit a certain refresh rate that is not supported by the board. Sometimes we can't even connect to the device. But we successful overcome them as we keep trying and improve our code.

One bug we find is that we didn't set the correct value of conversion for the minute part of our stopwatch. As it should be converting back to 00:00 after 59:59, our implementation lets it increment till 99:59 before reseting. This is a small glitch and we were able to fix it using a simple constraint in our code.

## Conclusion
In this lab, we, for the first time, designed and implemented a complete Verilog project from scratch, debugged in simulation, and tested it on the Nexys3 board. We gained experience in properly structuring the projects by separating functionalities into different modules.

A difficulty we encountered was setting up the correct signals to pass onto the Nexy3 board. We didn't notice that the inputs `an0`-`an3` to the 7-segment display were inverted initially, which took us a significant amount of time to figure out the issues through incremental debugging. The passage of signals between modules also confused us for a while when writing Verilog codes, which we resolved by coming up with test branches for each module before beginning to write the next one.

Overall, we're satisfied with the experience of this lab. A suggestion we have is that the classroom could have more redundant boards for backup, in case the boards of some groups malfunction during the lab.