Computer Architecture 2021
Assignment 1
Assignment 3 建置教學
After finishing setting up the Environment,I try to make in the tools folder and sim folder.
Unfortunately, some errors occured when I make in the sim folder.
So, I find the -faligned-new
and -fcf-protection=none
in the /srv32/verilator/include/verilated.mk
Now, it can work smoothly.
The hw.c is below.
The Makefile is below.
I found that printf
must contain \n
in the end, otherwise it can't work fine. Also, we should make at the root directory.
I found that dhrystone and cormark is in the sw
folder, so I create a foler to store hw.c and Makefile. At the root directory, I can use make hw3
and the result is following.
There are RAW data hazard as below.But I found that number_of_1bits function is not executed in the trace.log.
IF/ID | EX | WB |
---|---|---|
beqz a5,address | addi a4,a5,-1 | and a5,a5,a4 |
we can found that branch penalty is 2 cycle.
I have to check this note that jserv comment on my Lab1, so I decide to write a new program which calculating 2 bits at a time. Thw following is my new program.
Before I make, I expect that the cycles count of the new program will be much less than that of the version 1 program.The following is new program information.
The following is first written.
Based on the same input value(0xFFFFFFFF),the result is not as I expected.
I modify the code of version 2. The following is a code of modified version 2.
I do the loop unrolling for number_of_1bits function
Now,it look the same as version 1.Also,I found that the number of instruction of version 2 that it does not do the loop unrolling is 1541.After doing the loop unrolling, the number of instruction is 1510. It reduces to 31 intructions and 35 cycles.
This assignment gave me a better understanding of hardware operation. Using the GTKWave sofrware,I can choose signal wire that I want to observe.From this assignment 3,I learned srv32 how to work on 3 pipelines and how to handle data harzard.