Verilog Cheat Sheet

I/O Port

Template code for module's IO ports.

// ### AXI4-full slave signals (for BRAM Controller) ####
// *** Read address signals ***
input  wire [14:0] s_axi_dat_araddr,
input  wire [1:0]  s_axi_dat_arburst,
input  wire [3:0]  s_axi_dat_arcache,
input  wire [7:0]  s_axi_dat_arlen,
input  wire        s_axi_dat_arlock,
input  wire [2:0]  s_axi_dat_arprot,
output wire        s_axi_dat_arready,
input  wire [2:0]  s_axi_dat_arsize,
input  wire        s_axi_dat_arvalid,
 // *** Write address signals ***       
input  wire [14:0] s_axi_dat_awaddr,
input  wire [1:0]  s_axi_dat_awburst,
input  wire [3:0]  s_axi_dat_awcache,
input  wire [7:0]  s_axi_dat_awlen,
input  wire        s_axi_dat_awlock,
input  wire [2:0]  s_axi_dat_awprot,
output wire        s_axi_dat_awready,
input  wire [2:0]  s_axi_dat_awsize,
input  wire        s_axi_dat_awvalid,
// *** Write response signals ***
input  wire        s_axi_dat_bready,
output wire [1:0]  s_axi_dat_bresp,
output wire        s_axi_dat_bvalid,
// *** Read data signals ***    
output wire [31:0] s_axi_dat_rdata,
output wire        s_axi_dat_rlast,
input  wire        s_axi_dat_rready,
output wire [1:0]  s_axi_dat_rresp,
output wire        s_axi_dat_rvalid,
// *** Write data signals ***
input  wire [31:0] s_axi_dat_wdata,
input  wire        s_axi_dat_wlast,
output wire        s_axi_dat_wready,
input  wire [3:0]  s_axi_dat_wstrb,
input  wire        s_axi_dat_wvalid,
// ### AXI4-lite slave signals ###
// *** Write address signals ***
output wire        s_axi_awready,
input  wire [31:0] s_axi_awaddr,
input  wire        s_axi_awvalid,
// *** Write data signals ***
output wire        s_axi_wready,
input  wire [31:0] s_axi_wdata,
input  wire [3:0]  s_axi_wstrb,
input  wire        s_axi_wvalid,
// *** Write response signals ***
input  wire        s_axi_bready,
output wire [1:0]  s_axi_bresp,
output wire        s_axi_bvalid,
// *** Read address signals ***
output wire        s_axi_arready,
input  wire [31:0] s_axi_araddr,
input  wire        s_axi_arvalid,
// *** Read data signals ***    
input  wire        s_axi_rready,
output wire [31:0] s_axi_rdata,
output wire [1:0]  s_axi_rresp,
output wire        s_axi_rvalid,

// ### AXI4-stream slave port ###
output wire        s_axis_tready,
input wire [31:0]  s_axis_tdata,
input wire         s_axis_tvalid,
input wire         s_axis_tlast,
// ### AXI4-stream master port ###
input wire         m_axis_tready,
output wire [31:0] m_axis_tdata,
output wire        m_axis_tvalid,
output wire        m_axis_tlast,

// ### Input to control BRAM ###
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)  input wire         clka,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA RST" *)  input wire         rsta,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)   input wire         ena,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input wire [31:0]  addra,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)  input wire [31:0]  dina,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)   input wire [3:0]   wea,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output wire [31:0] douta,
// ### Output to control BRAM ###
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)  output wire        clka,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA RST" *)  output wire        rsta,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)   output wire        ena,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) output wire [31:0] addra,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)  output wire [31:0] dina,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)   output wire [3:0]  wea,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) input wire  [31:0] douta,
// ### Input to control BRAM ###
input wire         clka,
input wire         rsta,
input wire         ena,
input wire [31:0]  addra,
input wire [31:0]  dina,
input wire [3:0]   wea,
output wire [31:0] douta,
// ### Output to control BRAM ###
output wire        clka,
output wire        rsta,
output wire        ena,
output wire [31:0] addra,
output wire [31:0] dina,
output wire [3:0]  wea,
input wire  [31:0] douta,

---

Variable Declaration

Template code for module's variables.

// AXI slave
wire s_axi_arready;
wire [31:0] s_axi_araddr;
wire s_axi_arvalid; 
wire s_axi_awready;
wire [31:0] s_axi_awaddr;
wire s_axi_awvalid;  
wire s_axi_bready;
wire [1:0] s_axi_bresp;
wire s_axi_bvalid;
wire s_axi_rready;
wire [31:0] s_axi_rdata;
wire [1:0] s_axi_rresp;
wire s_axi_rvalid;
wire s_axi_wready;
wire [31:0] s_axi_wdata;
wire [3:0] s_axi_wstrb;
wire s_axi_wvalid;

wire s_axis_tready;
wire [7:0] s_axis_tdata;
wire s_axis_tvalid;
wire s_axis_tlast;

wire m_axis_tready;
wire [7:0] m_axis_tdata;
wire m_axis_tvalid;
wire m_axis_tlast;

wire clka;
wire rsta;
wire ena;
wire [31:0] addra;
wire [31:0] dina;
wire [3:0] wea;
wire [31:0] douta;

wire clkb;
wire rstb;
wire enb;
wire [31:0] addrb;
wire [31:0] dinb;
wire [3:0] web;
wire [31:0] doutb;

---

XPM Instantiation

Template code for XPM instantiation.

// xpm_fifo_sync: Synchronous FIFO
// Xilinx Parameterized Macro, version 2019.1
xpm_fifo_sync
#(
    .DOUT_RESET_VALUE("0"),    // String 
    .ECC_MODE("no_ecc"),       // String 
    .FIFO_MEMORY_TYPE("auto"), // String 
    .FIFO_READ_LATENCY(1),     // DECIMAL 
    .FIFO_WRITE_DEPTH(512),    // DECIMAL, depth 512 elemen 
    .FULL_RESET_VALUE(0),      // DECIMAL 
    .PROG_EMPTY_THRESH(10),    // DECIMAL 
    .PROG_FULL_THRESH(10),     // DECIMAL 
    .RD_DATA_COUNT_WIDTH(1),   // DECIMAL 
    .READ_DATA_WIDTH(2),       // DECIMAL, lebar data 2 bits 
    .READ_MODE("std"),         // String 
    .SIM_ASSERT_CHK(0),        // DECIMAL 
    .USE_ADV_FEATURES("1000"), // String, enable data valid 
    .WAKEUP_TIME(0),           // DECIMAL 
    .WRITE_DATA_WIDTH(2),      // DECIMAL, lebar data 2 bits 
    .WR_DATA_COUNT_WIDTH(1)    // DECIMAL 
) 
xpm_fifo_sync_ce
(
    .almost_empty(), 
    .almost_full(),
    .dbiterr(), 
    .empty(), 
    .full(), 
    .overflow(), 
    .prog_empty(), 
    .prog_full(), 
    .rd_data_count(), 
    .rd_rst_busy(), 
    .sbiterr(), 
    .underflow(), 
    .wr_ack(), 
    .wr_data_count(), 
    .wr_rst_busy(), 
    .injectdbiterr(1'b0), 
    .injectsbiterr(1'b0), 
    .sleep(1'b0), 

    .wr_clk(clk), // clk
    .rst(rst), // rst

    .din(din), // din
    .wr_en(wr_en), // wr_en

    .rd_en(rd_en), // rd_en
    .dout(dout), // dout
    .data_valid(valid) // valid
);

// xpm_fifo_axis: AXI Stream FIFO
// Xilinx Parameterized Macro, version 2018.3
xpm_fifo_axis
#(
    .CDC_SYNC_STAGES(2),                 // DECIMAL
    .CLOCKING_MODE("common_clock"),      // String
    .ECC_MODE("no_ecc"),                 // String
    .FIFO_DEPTH(256),                    // DECIMAL, depth 256 elemen 
    .FIFO_MEMORY_TYPE("auto"),           // String
    .PACKET_FIFO("false"),               // String
    .PROG_EMPTY_THRESH(10),              // DECIMAL
    .PROG_FULL_THRESH(10),               // DECIMAL
    .RD_DATA_COUNT_WIDTH(1),             // DECIMAL
    .RELATED_CLOCKS(0),                  // DECIMAL
    .SIM_ASSERT_CHK(0),                  // DECIMAL
    .TDATA_WIDTH(32),                    // DECIMAL, data width 32 bit
    .TDEST_WIDTH(1),                     // DECIMAL
    .TID_WIDTH(1),                       // DECIMAL
    .TUSER_WIDTH(1),                     // DECIMAL
    .USE_ADV_FEATURES("0004"),           // String, write data count
    .WR_DATA_COUNT_WIDTH(9)              // DECIMAL, width log2(256)+1=9 
)
xpm_fifo_axis_0
(
    .almost_empty_axis(), 
    .almost_full_axis(), 
    .dbiterr_axis(), 
    .prog_empty_axis(), 
    .prog_full_axis(), 
    .rd_data_count_axis(), 
    .sbiterr_axis(), 
    .injectdbiterr_axis(1'b0), 
    .injectsbiterr_axis(1'b0), 

    .s_aclk(aclk), // aclk
    .m_aclk(aclk), // aclk
    .s_aresetn(aresetn), // aresetn
    
    .s_axis_tready(s_axis_tready), // ready    
    .s_axis_tdata(s_axis_tdata), // data
    .s_axis_tvalid(s_axis_tvalid), // valid
    .s_axis_tdest(1'b0), 
    .s_axis_tid(1'b0), 
    .s_axis_tkeep(4'b1), 
    .s_axis_tlast(1'b0), 
    .s_axis_tstrb(4'b1), 
    .s_axis_tuser(1'b0), 
    
    .m_axis_tready(m_axis_tready), // ready  
    .m_axis_tdata(m_axis_tdata), // data
    .m_axis_tvalid(m_axis_tvalid), // valid
    .m_axis_tdest(), 
    .m_axis_tid(), 
    .m_axis_tkeep(), 
    .m_axis_tlast(), 
    .m_axis_tstrb(), 
    .m_axis_tuser(),  
    
    .wr_data_count_axis(wr_data_count) // data count
);

// xpm_memory_spram: Single Port RAM
// Xilinx Parameterized Macro, version 2019.1
xpm_memory_spram
#(        
    // Common module parameters
    .MEMORY_SIZE(32768),                 // DECIMAL, ukuran memory: 1024x32bit= 32768 bits
    .MEMORY_PRIMITIVE("auto"),           // String, "auto", "distributed", "block" or "ultra"
    .MEMORY_INIT_FILE("preamble_rom.mem"),
    .MEMORY_INIT_PARAM("0"),             // String      
    .USE_MEM_INIT(1),                    // DECIMAL
    .WAKEUP_TIME("disable_sleep"),       // String
    .MESSAGE_CONTROL(0),                 // DECIMAL
    .AUTO_SLEEP_TIME(0),                 // DECIMAL, 0=Disable auto-sleep feature          
    .ECC_MODE("no_ecc"),                 // String
    .MEMORY_OPTIMIZATION("true"),        // String              
    .CASCADE_HEIGHT(0),                  // DECIMAL
    .SIM_ASSERT_CHK(0),                  // DECIMAL; 0=disable simulation messages, 1=enable simulation messages    
			
    // Port A module parameters
    .WRITE_DATA_WIDTH_A(32),             // DECIMAL, lebar data: 32-bit
    .READ_DATA_WIDTH_A(32),              // DECIMAL, lebar data: 32-bit
    .BYTE_WRITE_WIDTH_A(32),             // DECIMAL
    .ADDR_WIDTH_A(10),                   // DECIMAL, lebar address: clog2(32768/32)=clog2(1024)= 10 elemen
    .READ_RESET_VALUE_A("0"),            // String
    .READ_LATENCY_A(2),                  // DECIMAL
    .WRITE_MODE_A("write_first"),        // String
    .RST_MODE_A("SYNC")                  // String
)
xpm_memory_spram_0
(
    .sleep(1'b0),
		
    .clka(aclk),
    .rsta(areset),
    .ena(bram_ena),
    .wea(bram_wea),      
    .addra(bram_addra),
    .dina(bram_dina),
    .douta(bram_douta),

    .regcea(1'b1), //do not change
    .injectsbiterra(1'b0), //do not change
    .injectdbiterra(1'b0), //do not change   
    .sbiterra(), //do not change
    .dbiterra() //do not change
);

// xpm_memory_tdpram: True Dual Port RAM
// Xilinx Parameterized Macro, version 2018.3
xpm_memory_tdpram
#(
    // Common module parameters
    .MEMORY_SIZE(16384),                 // DECIMAL, size: 2048x8bit= 16384 bits
    .MEMORY_PRIMITIVE("auto"),           // String
    .CLOCKING_MODE("common_clock"),      // String, "common_clock"
    .MEMORY_INIT_FILE("none"),           // String
    .MEMORY_INIT_PARAM("0"),             // String      
    .USE_MEM_INIT(1),                    // DECIMAL
    .WAKEUP_TIME("disable_sleep"),       // String
    .MESSAGE_CONTROL(0),                 // DECIMAL
    .AUTO_SLEEP_TIME(0),                 // DECIMAL          
    .ECC_MODE("no_ecc"),                 // String
    .MEMORY_OPTIMIZATION("true"),        // String              
    .USE_EMBEDDED_CONSTRAINT(0),         // DECIMAL
	
    // Port A module parameters
    .WRITE_DATA_WIDTH_A(8),              // DECIMAL, lebar data: 8-bit
    .READ_DATA_WIDTH_A(8),               // DECIMAL, lebar data: 8-bit
    .BYTE_WRITE_WIDTH_A(8),              // DECIMAL
    .ADDR_WIDTH_A(11),                   // DECIMAL, clog2(16384/8)=clog2(2048)= 11
    .READ_RESET_VALUE_A("0"),            // String
    .READ_LATENCY_A(1),                  // DECIMAL
    .WRITE_MODE_A("write_first"),        // String
    .RST_MODE_A("SYNC"),                 // String
	
    // Port B module parameters  
    .WRITE_DATA_WIDTH_B(8),              // DECIMAL, lebar data: 8-bit
    .READ_DATA_WIDTH_B(8),               // DECIMAL, lebar data: 8-bit
    .BYTE_WRITE_WIDTH_B(8),              // DECIMAL
    .ADDR_WIDTH_B(11),                   // DECIMAL, clog2(16384/8)=clog2(2048)= 11
    .READ_RESET_VALUE_B("0"),            // String
    .READ_LATENCY_B(1),                  // DECIMAL
    .WRITE_MODE_B("write_first"),        // String
    .RST_MODE_B("SYNC")                  // String
)
xpm_memory_tdpram_0
(
    .sleep(1'b0),
    .regcea(1'b1), //do not change
    .injectsbiterra(1'b0), //do not change
    .injectdbiterra(1'b0), //do not change   
    .sbiterra(), //do not change
    .dbiterra(), //do not change
    .regceb(1'b1), //do not change
    .injectsbiterrb(1'b0), //do not change
    .injectdbiterrb(1'b0), //do not change              
    .sbiterrb(), //do not change
    .dbiterrb(), //do not change
    
    // Port A module ports
    .clka(aclk),
    .rsta(~aresetn),
    .ena(ena),
    .wea(wea),
    .addra(addra),
    .dina(dina),                    
    .douta(douta),
    
    // Port B module ports
    .clkb(clkb),
    .rstb(rstb),
    .enb(enb),
    .web(web),
    .addrb(addrb),
    .dinb(dinb),
    .doutb(doutb)
);

---

Module Instantiation

Template code for module instantiation.

// AXI BRAM controller
axi_bram_ctrl_0 axi_bram_ctrl_0_inst
(
    .s_axi_aclk(aclk),
    .s_axi_aresetn(aresetn),
    .s_axi_araddr(s_axi_dat_araddr),
    .s_axi_arburst(s_axi_dat_arburst),
    .s_axi_arcache(s_axi_dat_arcache),
    .s_axi_arlen(s_axi_dat_arlen),
    .s_axi_arlock(s_axi_dat_arlock),
    .s_axi_arprot(s_axi_dat_arprot),
    .s_axi_arready(s_axi_dat_arready),
    .s_axi_arsize(s_axi_dat_arsize),
    .s_axi_arvalid(s_axi_dat_arvalid),
    .s_axi_awaddr(s_axi_dat_awaddr),
    .s_axi_awburst(s_axi_dat_awburst),
    .s_axi_awcache(s_axi_dat_awcache),
    .s_axi_awlen(s_axi_dat_awlen),
    .s_axi_awlock(s_axi_dat_awlock),
    .s_axi_awprot(s_axi_dat_awprot),
    .s_axi_awready(s_axi_dat_awready),
    .s_axi_awsize(s_axi_dat_awsize),
    .s_axi_awvalid(s_axi_dat_awvalid),
    .s_axi_bready(s_axi_dat_bready),
    .s_axi_bresp(s_axi_dat_bresp),
    .s_axi_bvalid(s_axi_dat_bvalid),
    .s_axi_rdata(s_axi_dat_rdata),
    .s_axi_rlast(s_axi_dat_rlast),
    .s_axi_rready(s_axi_dat_rready),
    .s_axi_rresp(s_axi_dat_rresp),
    .s_axi_rvalid(s_axi_dat_rvalid),
    .s_axi_wdata(s_axi_dat_wdata),
    .s_axi_wlast(s_axi_dat_wlast),
    .s_axi_wready(s_axi_dat_wready),
    .s_axi_wstrb(s_axi_dat_wstrb),
    .s_axi_wvalid(s_axi_dat_wvalid),
    .bram_addr_a(addra),
    .bram_clk_a(clka),
    .bram_wrdata_a(dina),
    .bram_rddata_a(bram_rddata_a),
    .bram_en_a(ena),
    .bram_rst_a(rsta),
    .bram_we_a(wea)
);

// Block memory generator
blk_mem_gen_0 blk_mem_gen_0_inst
(
    .clka(clka),
    .rsta(rsta),
    .ena(ena),
    .addra(addra),
    .dina(dina),
    .douta(douta),
    .wea(wea),
    .rsta_busy(), // NC
    .clkb(clkb),
    .rstb(rstb),
    .enb(enb),
    .addrb(addrb),
    .dinb(dinb),
    .doutb(doutb),
    .web(web),
    .rstb_busy() // NC
);

---

Testbench

Template code for testbench.

`timescale 1ns / 1ps

module module_tb();
    localparam T = 10;
    
    reg aclk;
    reg aresetn;
    
    // AXI slave
    wire s_axi_arready;
    reg [31:0] s_axi_araddr;
    reg s_axi_arvalid; 
    wire s_axi_awready;
    reg [31:0] s_axi_awaddr;
    reg s_axi_awvalid;  
    reg s_axi_bready;
    wire [1:0] s_axi_bresp;
    wire s_axi_bvalid;
    reg s_axi_rready;
    wire [31:0] s_axi_rdata;
    wire [1:0] s_axi_rresp;
    wire s_axi_rvalid;
    wire s_axi_wready;
    reg [31:0] s_axi_wdata;
    reg [3:0] s_axi_wstrb;
    reg s_axi_wvalid;
    
    // AXI TX FIFO
    wire s_axi_tx_fifo_arready;
    reg [31:0] s_axi_tx_fifo_araddr;
    reg s_axi_tx_fifo_arvalid; 
    wire s_axi_tx_fifo_awready;
    reg [31:0] s_axi_tx_fifo_awaddr;
    reg s_axi_tx_fifo_awvalid;  
    reg s_axi_tx_fifo_bready;
    wire [1:0] s_axi_tx_fifo_bresp;
    wire s_axi_tx_fifo_bvalid;
    reg s_axi_tx_fifo_rready;
    wire [31:0] s_axi_tx_fifo_rdata;
    wire [1:0] s_axi_tx_fifo_rresp;
    wire s_axi_tx_fifo_rvalid;
    wire s_axi_tx_fifo_wready;
    reg [31:0] s_axi_tx_fifo_wdata;
    reg [3:0] s_axi_tx_fifo_wstrb;
    reg s_axi_tx_fifo_wvalid;

    // AXI RX FIFO
    wire s_axi_rx_fifo_arready;
    reg [31:0] s_axi_rx_fifo_araddr;
    reg s_axi_rx_fifo_arvalid; 
    wire s_axi_rx_fifo_awready;
    reg [31:0] s_axi_rx_fifo_awaddr;
    reg s_axi_rx_fifo_awvalid;  
    reg s_axi_rx_fifo_bready;
    wire [1:0] s_axi_rx_fifo_bresp;
    wire s_axi_rx_fifo_bvalid;
    reg s_axi_rx_fifo_rready;
    wire [31:0] s_axi_rx_fifo_rdata;
    wire [1:0] s_axi_rx_fifo_rresp;
    wire s_axi_rx_fifo_rvalid;
    wire s_axi_rx_fifo_wready;
    reg [31:0] s_axi_rx_fifo_wdata;
    reg [3:0] s_axi_rx_fifo_wstrb;
    reg s_axi_rx_fifo_wvalid;
    
    // AXI TX
    wire s_axi_tx_arready;
    reg [31:0] s_axi_tx_araddr;
    reg s_axi_tx_arvalid; 
    wire s_axi_tx_awready;
    reg [31:0] s_axi_tx_awaddr;
    reg s_axi_tx_awvalid;  
    reg s_axi_tx_bready;
    wire [1:0] s_axi_tx_bresp;
    wire s_axi_tx_bvalid;
    reg s_axi_tx_rready;
    wire [31:0] s_axi_tx_rdata;
    wire [1:0] s_axi_tx_rresp;
    wire s_axi_tx_rvalid;
    wire s_axi_tx_wready;
    reg [31:0] s_axi_tx_wdata;
    reg [3:0] s_axi_tx_wstrb;
    reg s_axi_tx_wvalid;

    // AXI RX
    wire s_axi_rx_arready;
    reg [31:0] s_axi_rx_araddr;
    reg s_axi_rx_arvalid; 
    wire s_axi_rx_awready;
    reg [31:0] s_axi_rx_awaddr;
    reg s_axi_rx_awvalid;  
    reg s_axi_rx_bready;
    wire [1:0] s_axi_rx_bresp;
    wire s_axi_rx_bvalid;
    reg s_axi_rx_rready;
    wire [31:0] s_axi_rx_rdata;
    wire [1:0] s_axi_rx_rresp;
    wire s_axi_rx_rvalid;
    wire s_axi_rx_wready;
    reg [31:0] s_axi_rx_wdata;
    reg [3:0] s_axi_rx_wstrb;
    reg s_axi_rx_wvalid;
    
    // S_AXIS
    wire s_axis_tready;
    reg [7:0] s_axis_tdata;
    reg s_axis_tvalid;
    reg s_axis_tlast;

    // M_AXIS
    reg m_axis_tready;
    wire [7:0] m_axis_tdata;
    wire m_axis_tvalid;
    wire m_axis_tlast;

    // Interrupt
    wire tx_itrpt;
    reg s2mm_introut;
    wire rx_itrpt;

    reg [31:0] data[0:1000];
    integer i = 0, j = 0;

    always
    begin
        aclk = 0;
        #(T/2);
        aclk = 1;
        #(T/2);
    end

    initial
    begin
        $readmemh("D:/Repository/matlab/data.dat", data);

        s_axi_awaddr = 0;
        s_axi_awvalid = 0;
        s_axi_wstrb = 0;
        s_axi_wdata = 0;
        s_axi_wvalid = 0;
        s_axi_bready = 1;
        s_axi_araddr = 0;
        s_axi_arvalid = 0;
        s_axi_rready = 0;
        
        s_axi_tx_fifo_awaddr = 0;
        s_axi_tx_fifo_awvalid = 0;
        s_axi_tx_fifo_wstrb = 0;
        s_axi_tx_fifo_wdata = 0;
        s_axi_tx_fifo_wvalid = 0;
        s_axi_tx_fifo_bready = 1;
        s_axi_tx_fifo_araddr = 0;
        s_axi_tx_fifo_arvalid = 0;
        s_axi_tx_fifo_rready = 1;
        
        s_axi_rx_fifo_awaddr = 0;
        s_axi_rx_fifo_awvalid = 0;
        s_axi_rx_fifo_wstrb = 0;
        s_axi_rx_fifo_wdata = 0;
        s_axi_rx_fifo_wvalid = 0;
        s_axi_rx_fifo_bready = 1;
        s_axi_rx_fifo_araddr = 0;
        s_axi_rx_fifo_arvalid = 0;
        s_axi_rx_fifo_rready = 1;
        
        s_axi_tx_awaddr = 0;
        s_axi_tx_awvalid = 0;
        s_axi_tx_wstrb = 0;
        s_axi_tx_wdata = 0;
        s_axi_tx_wvalid = 0;
        s_axi_tx_bready = 1;
        s_axi_tx_araddr = 0;
        s_axi_tx_arvalid = 0;
        s_axi_tx_rready = 0;
        
        s_axi_rx_awaddr = 0;
        s_axi_rx_awvalid = 0;
        s_axi_rx_wstrb = 0;
        s_axi_rx_wdata = 0;
        s_axi_rx_wvalid = 0;
        s_axi_rx_bready = 1;
        s_axi_rx_araddr = 0;
        s_axi_rx_arvalid = 0;
        s_axi_rx_rready = 0;

        s_axis_tdata = 0;
        s_axis_tvalid = 0;
        s_axis_tlast = 0;
        m_axis_tready = 1;
        
        s2mm_introut = 0;
        
        aresetn = 0;
        #(T*50);
        aresetn = 1;
        #(T*50);
        
        axi_write(32'h00000000, 168);
        
        // Send data to AXIS
        s_axis_tvalid = 1;
        for (i = 0; i < 1000; i = i+1)
        begin
            s_axis_tdata = data[i];
            if (i == 1000-1)
            begin
                s_axis_tlast = 1;
            end
            #T;
        end        
        s_axis_tvalid = 0;
        s_axis_tlast = 0;
        #(T*10);

    end

    always @(posedge aclk)
    begin
        if (m_axis_tvalid)
        begin
            $display("%b", m_axis_tdata); 
        end
    end
    
    // Read TX buffer descriptor
    always @(posedge aclk)
    begin
        if (tx_itrpt)
        begin
            #(T*5); 
            axi_read_tx_fifo(32'h0000000c);
        end
    end

    // Generate stream to memory mapped interrupt
    always @(posedge aclk)
    begin
        if (m_axis_tlast)
        begin
            s2mm_introut = 1;
            #(T*10);
            s2mm_introut = 0;
            while (m_axis_tlast)
            begin
                #T;
            end           
        end
    end

    task axi_write;
        input [31:0] awaddr;
        input [31:0] wdata; 
        begin
            // *** Write address ***
            s_axi_awaddr = awaddr;
            s_axi_awvalid = 1;
            #T;
            s_axi_awvalid = 0;
            // *** Write data ***
            s_axi_wdata = wdata;
            s_axi_wstrb = 4'hf;
            s_axi_wvalid = 1; 
            #T;
            s_axi_wvalid = 0;
            #T;
        end
    endtask
    task axi_read;
        input [31:0] araddr;
        begin
            // *** Read address ***
            s_axi_araddr = araddr;
            s_axi_arvalid = 1;
            #T;
            s_axi_arvalid = 0;
            #T;
        end
    endtask

    task axi_write_tx_fifo;
        input [31:0] awaddr;
        input [31:0] wdata; 
        begin
            // *** Write address ***
            s_axi_tx_fifo_awaddr = awaddr;
            s_axi_tx_fifo_awvalid = 1;
            #T;
            s_axi_tx_fifo_awvalid = 0;
            // *** Write data ***
            s_axi_tx_fifo_wdata = wdata;
            s_axi_tx_fifo_wstrb = 4'hf;
            s_axi_tx_fifo_wvalid = 1; 
            #T;
            s_axi_tx_fifo_wvalid = 0;
            #T;
        end
    endtask
    task axi_read_tx_fifo;
        input [31:0] araddr;
        begin
            // *** Read address ***
            s_axi_tx_fifo_araddr = araddr;
            s_axi_tx_fifo_arvalid = 1;
            #T;
            s_axi_tx_fifo_arvalid = 0;
            #T;
        end
    endtask

    task axi_write_rx_fifo;
        input [31:0] awaddr;
        input [31:0] wdata; 
        begin
            // *** Write address ***
            s_axi_rx_fifo_awaddr = awaddr;
            s_axi_rx_fifo_awvalid = 1;
            #T;
            s_axi_rx_fifo_awvalid = 0;
            // *** Write data ***
            s_axi_rx_fifo_wdata = wdata;
            s_axi_rx_fifo_wstrb = 4'hf;
            s_axi_rx_fifo_wvalid = 1; 
            #T;
            s_axi_rx_fifo_wvalid = 0;
            #T;
        end
    endtask 
    task axi_read_rx_fifo;
        input [31:0] araddr;
        begin
            // *** Read address ***
            s_axi_rx_fifo_araddr = araddr;
            s_axi_rx_fifo_arvalid = 1;
            #T;
            s_axi_rx_fifo_arvalid = 0;
            #T;
        end
    endtask

    task axi_tx_write;
        input [31:0] awaddr;
        input [31:0] wdata; 
        begin
            // *** Write address ***
            s_axi_tx_awaddr = awaddr;
            s_axi_tx_awvalid = 1;
            #T;
            s_axi_tx_awvalid = 0;
            // *** Write data ***
            s_axi_tx_wdata = wdata;
            s_axi_tx_wstrb = 4'hf;
            s_axi_tx_wvalid = 1; 
            #T;
            s_axi_tx_wvalid = 0;
            #T;
        end
    endtask
    task axi_tx_read;
        input [31:0] araddr;
        begin
            // *** Read address ***
            s_axi_tx_araddr = araddr;
            s_axi_tx_arvalid = 1;
            #T;
            s_axi_tx_arvalid = 0;
            #T;
        end
    endtask

    task axi_rx_write;
        input [31:0] awaddr;
        input [31:0] wdata; 
        begin
            // *** Write address ***
            s_axi_rx_awaddr = awaddr;
            s_axi_rx_awvalid = 1;
            #T;
            s_axi_rx_awvalid = 0;
            // *** Write data ***
            s_axi_rx_wdata = wdata;
            s_axi_rx_wstrb = 4'hf;
            s_axi_rx_wvalid = 1; 
            #T;
            s_axi_rx_wvalid = 0;
            #T;
        end
    endtask
    task axi_rx_read;
        input [31:0] araddr;
        begin
            // *** Read address ***
            s_axi_rx_araddr = araddr;
            s_axi_rx_arvalid = 1;
            #T;
            s_axi_rx_arvalid = 0;
            #T;
        end
    endtask
    
endmodule

---