# Memory
###### tags: `CA`
[link](https://hackmd.io/@sysprog/HkW3Dr1Rb?type=view)

**locality**
* temporal
* if accessed, will access again soon
* loop
* spatial
* if accessed, will access others around it
* array

**DRAM**
main memory
電荷儲存於電容(會漏電，所以要refresh)
小、慢

**SRAM**
cache
反向gate
快、大(4~6電晶體)
## Cache
> between cache and main memory

**split cache** = instruction cache + data cache
可同時進行
有較大的bandwidth，克服miss增加的壞處
有較佳的hit
**combined cache**
不能同時進行
### Cache Write
#### Hit
* write through
寫入cache，也寫入memory
> write buffer改善write through

* write back
新的值只會被寫入cache中，被置換時，修改過($\therefore$ 需要dirty bit)的才會被寫回較低的memory level

#### Handling Miss
* Miss penalty grows as block size does
* write allocate
* when we bring the block into the cache after a write miss
* 在cache中配置block，並由memory中取得所需要的，再將其寫入配置的block中
* no write allocate(write around)
* only change main memory after a write miss
* 更新再memory中該block需要被寫入的部分，不在cache配置
* 必須將此cache block設為invalid，$\because$ no fresh
:::success
write back with write allocate
> Accessing same address many times $\Rightarrow$ cache it

write through with no write allocate
> Infrequent/random writes $\Rightarrow$ don’t bother caching it
:::
#### word address 找 Hit/Miss
* word address 除以一個block有幾個word，得到 block address
* 再求 tag 和 index，就把 block address 除以 cache(set) 有幾個 block(block 總數)
* 商數 $\Rightarrow$ tag
* 餘數 $\Rightarrow$ index, set
:::success
**Think**
index 是每個人要坐的位子，tag 是每個人的編號
1. 先找位子(index)，編號(tag)一樣，代表現在位子上做的是自己，所以 HIT
2. 若位子(index)一樣，編號(tag)不一樣，表示上面做的不是自己，所以 MISS
2-way 表示每個人被分配到一個裡面有 2 個位子的 set，set 裡面有 2 個位子想做哪都可以
:::
> [100交大](https://www.ptt.cc/bbs/Grad-ProbAsk/M.1511357846.A.14D.html)
### Directed Mapped
* Each memory block is mapped to exactly one slot in the cache
* Every block has only one home
* Hash function


**comparison**

### Set associativity
* Fully : blocks can go anywhere
* Direct-mapped : blocks go in one specific location
* N-way : cache split into sets, each of which have n slots to place memory blocks

### AMAT
:::info
:::
#### Hit time

* cache size $\downarrow$ $\Rightarrow$ hit time $\downarrow$
* associativity $\uparrow$ $\Rightarrow$ hit time $\uparrow$

#### Miss rate
* Comolusory(cold start) miss
* Inscrease block size
* too large blocks could increase miss rate
* Capacity miss
* Increase cache size
* may increase hit time
* Conflict miss
* Increase associativity
* (to fully associative) may increase hit time

#### Minimising AMAT
To make AMAT small
* directed mapped caches have small hit time
* fully associative caches have a low miss rate
* small blocks help with lowering miss penalty
* $\therefore$ many opportunties to store data
* Multilevel cache
* $L1$$ : focus on low hit time(fast access)
* minimize HT to achieve shorter clock cycle
* $L2$$, $L3$$ : focus on low miss rate
* as much as possible avoid reaching to main memory


### Local vs. Global Miss Rate
**Local miss rate** : Fraction of references to one level of a cache that miss
**Global miss rate** : Fraction of all references that miss in all levels of a multilevel cache
> Global MR is the product of all local MRs　

## Virtual Memory

> between main memory and disk

設計動機
-- 允許多個程式能夠有效率且安全的分享記憶體
-- 消除因主記憶體過小所造成程式的限制

1. only fully(有最小的page fault)
2. only write back(write through花太多時間)
3. only LRU
:::success
32 bit virtual address
4KB pages $\Rightarrow$ offset = 12
(page size $\rightarrow$ offset)
$\therefore$ index = 32 - 12 = 20
$\because$ 4B per page table entry
$\therefore$ page table size = $2^{20}\times 4$ = 4MB
:::

### Address
* virtual address藉由硬體或軟體轉譯成physical address
* physical address 存取main memory
* page offset : 決定a page的大小

### TLB
fully
加速virtual address轉換成physical address