###### tags: `computer organization` `test` `thu`
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# 110期中-解析
## 1. Please calculate the number of FPU of Top1 and Top4 Supercomputers respectively.
### $$R_{peak} = Cores \cdot CPU\ Frequency \cdot FPU$$
### $$1\ TFlop/s = 1000\ GFlop/s$$
### FPU Should be an integer
### 題目

### Solution
Rank 1:
$537,212.0 \cdot 1000 = (7,630,848) \cdot (2.2) \cdot FPU$
$537,212,000 = (7,630,848) \cdot (2.2) \cdot FPU$
$FPU = 32$
Rank 2:
$125,435.9 \cdot 1000 = (10,649,600) \cdot (1.45) \cdot FPU$
$125,435,900 = (10,649,600) \cdot (1.45) \cdot FPU$
$FPU = 8.12 = 8$
## 2. Suppose a new CPU has 70% of capacitive load of old CPU, 30% voltage and 20% frequency reduction of old CPU. Please calculate the power of a new CPU in terms of how many times of old CPU.
### $$Power\ = \ Capacitive\ load \times Voltage^2 \times Frequency$$
### Solution
$$Power = 0.7 \cdot 0.7^2 \cdot 0.8 = 0.2744$$
## 3. Alternative compiled code sequences using instructions in classes A, B, C, D and E in the following table. Please identify which code sequence will get smaller average CPI than the other?
| Class | A | B | C | D | E |
| ----- | ---- | --- | ---- | - | - |
| CPI for class | 1 | 2 | 3 | 4 | 5 |
| IC in sequence 1 | 3 | 6 | 5 | 6 | 4 |
| IC in sequence 2 | 4 | 7 | 3 | 4 | 5 |
- IC in sequence 1:
$$\frac{(1\cdot 3+2\cdot 6+3\cdot 5+4\cdot 6+5\cdot4)}{(3+6+5+6+4)}=3.08$$
- IC in sequence 2:
$$\frac{(1\cdot 4+2\cdot 7+3\cdot 3+4\cdot 4+5\cdot5)}{(4+7+3+4+5)}=2.95$$
- IC in sequence 2 is smaller than other
## 4. 請說明使用Big endian and Little endian方法是如何分別儲存 $(AB12EF78)_H$此4 Bytes資料於記憶體`0000 0001 0002 0003`位址內?
| 順序 | big | small |
|:----:|:----:|:-----:|
| 3 | 78 | AB |
| 2 | EF | 12 |
| 1 | 12 | EF |
|0 | AB | 78 |
## 5. 請說明指令`jal`與`jr`的用途與差異。
`jal`: 用於主函式跳到子函式,保存address到$ra, j指令$
`jr`: 用於子函式跳回主函式,跳回$ra暫存器的值address, r指令$
## 6. 此為題組
### a. MIPS沒有暫存器搬移(`move`)指令。請說明如何藉由其他指令達到暫存器搬移動功能。
- `move`:
使用`add`指令與0暫存器$zero實作,將欲移動資料$s1加上0 $zero,放到目的暫存器$t0
```assembly
add $t0,$s1,$zero
```
### b. 同樣地,MIPS沒有比較小於後跳躍(`blt`)的指令。請說明如何藉由`slt`與`bne`達到相同的功能。 (可使用`$s1`, `$s2`, `$zero`)
- `blt`:
使用`slt`與`bne`,假設$s1<$s2就要跳到L
```assembly
slt $t0,$s1,$s2
bne $t0,$zero,L
```
=> `blt $s1,$s2,L`
## 7. 此為題組
### a. 請用圖示說明MIPS的定址法(Addressing): Register Addressing、Base Addressing、PC-Relative Addressing 及Pseudo direct Addressing。(搭配MIPS R-I-J指令格式解釋)
- MIPS addressing mode

1. i
2. r
3. i
4. i
5. j
### b. 說明Base Addressing, PC-Relative Addressing的差異。
- Base Addressing和PC-Relative Addressing的差異在於Base Addressing 在計算位址時是暫存器加上指令常數。
- PC-Relative Addressing 在計算位址時則是PC加上指令常數。
- Base Addressing和PC-Relative Addressing的差異在於Base Addressing 在計算位址時是暫存器加上指令常數。PC-Relative Addressing 在計算位址時則是PC加上指令常數。
### c. 為何Immediate Addressing最有效率?
* immediate Addressing最有效率的原因是不需要去找位址。
#### 參[筆記-Chapter 2](/2bLoHpJmS9WU81IlOeBHvQ)
## 8.何為三種Pipeline Hazards,與forwarding(前饋機制)請詳述。請問下列的程式碼是否有任何Hazard,如果有請列出,並敘述如何改善?
```assembly=
lw $t1, 0 ( $t0 )
lw $t2, 4( $t0 )
add $t3, $t1, $t2
sw $t3, 12( $t0 )
lw $t4, 8( $t0 )
add $t5, $t1, $t4
sw $t5, 16( $t0 )
```
#### (1) structure hazard: A require resource is busy.
#### (2) data hazard: Need to wait for previous instruction to complete its data read write.
#### (3) control hazard: Deciding on control action depends on previous instruction (beq, bne)
#### Forwarding: 不等到第一個指令將結果寫回,直接在第一個指令完成 Execution 時將結果傳送給第二個指令的 Execution Input 。
第二道指令和第三道指令中間會產生data hazard,可運用stall技術改善
第三道指令和第四道指令中間會產生data hazard,可用forwarding技術改善
第五道指令和第六道指令中間會產生data hazard,可運用stall技術改善
第六道指令和第七道指令中間會產生data hazard,可用forwarding技術改善
## 9. Please list at least five components for constructing a MIPS processor.
ALU, Register Mux, Data memory, Sign-extend
## 10. We have a processor with the following components, please draw the data path on those components and list all control flag values (Gray part) for `lw` and `beq` instructions, respectively(個別地).

### A. `beq rs, rt, value` (note: branch if rs=rt)

- RegDst:X
- RegWrite:0
- ALUSrc:0
- PCsrc:1
- MemRead:0
- MemWrite:0
- MemtoReg:X
- ALUOp:01
- ALU control:0110
### B. `lw rt, offset(rs)`

- RegDst:0
- RegWrite:1
- ALUSrc:1
- PCsrc:0, if Zero=1, otherwise 0
- MemRead:1
- MemWrite:0
- MemtoReg:1
- ALUOp:00
- ALU control:0010
