# Quiz5 of Computer Architecture (2021 Fall)
:::info
:information_source: General Information
* You are allowed to read **[lecture materials](http://wiki.csie.ncku.edu.tw/arch/schedule)**.
* That is, an open book exam.
* We are using the honor system during this quiz, and would like you to accept the following:
1. You will not share the quiz with anyone.
2. You will not discuss the material on the quiz with anyone until after solutions are released.
* Each answer has `5` points.
* :timer_clock: 09:10 ~ 10:00 AM on Dec 7, 2021
:::
## Problem `A`
Consider the G circuit, depicted on the following.
Since the G circuit is currently only combinational, we know exactly what to improve: Pipeline it.
1. We decide to start small with a **two-stage pipeline**. Using the diagram below, please show a two-stage pipeline with maximal throughput using a minimum number of registers. Calculate the overall throughput and latency of your circuit.
* Latency (ns): __ A01 __
* Throughput ($\frac{1}{ns}$): __ A02 __
> * A01 = ?
> * A02 = ?
2. Now, we decide to add an additional stage. Using the diagram below, please show a **three-stage pipeline** with maximal throughput using a minimum number of registers. Calculate the overall throughput and latency of your circuit.
* Latency (ns): __ A03 __
* Throughput ($\frac{1}{ns}$): __ A04 __
> * A03 = ?
> * A04 = ?
3. Then, think of the maximalthroughput pipeline. Using the diagram below, please show a pipeline that maximizes the throughput using a minimum number of registers. Calculate the latency and throughput of our circuit. You should use the smallest number of pipeline stages required to achieve maximum throughput.
* Latency (ns): __ A05 __
* Throughput ($\frac{1}{ns}$): __ A06 __
> * A05 = ?
> * A06 = ?
---
## Problem `B`
Assume that we are trying to build a RISC-V processor. For the reference purpose, there are two 5-stage (`IF`, `DEC`, `EXE`, `MEM`, `WB`) bypassing processors. However, they are a little broken. The processors are as follows:
* **Processor 1**: A defective 5 stage bypassing processor which does not annul instructions following branches.
* **Processor 2**: A defective 5 stage bypassing processor that reads all values bypassed back as 0 but reads correctly from the register file.
Known properties:
* Both processors always predict that branches are not taken (they always fetch from `PC + 4`).
* Both processors determine the direction of the branch in the `EXE` stage.
We try this simple RISC-V looping code on both of these processors. Assume at the start of the code that `x2` is set to some number greater than `0` and that all the other registers are set to `0`.
```cpp
L1: addi x1, x2, -4
bnez x1, L1
slli x3, x1, 1
lw x2, 0x100(x0)
. = 0x100
.word 0x4
```
1. If we had a fully working 5 stage bypassing processor, which always fetches from `PC + 4` and annuls instructions following taken branches, how many cycles would it take for one iteration of the loop? Assume that the `bnez` is taken. Provide the number of cycles per loop iteration.
* You may use the pipeline diagrams below to help you answer the question, but you are not required to fill them out.
* number of cycles per loop iteration = __ B01 __
> * B01 = ?
2. If we pass the number `0x10` into `x2`, by the time the second iteration's `addi` reaches `EXE`, what value will be passed to `x1` for each of the two defective processors? If the loop does not make it to a second iteration's `addi`, write `N/A`.
* You may use the pipeline diagrams below to help you answer the question, but you are not required to fill them out.
* Processor 1's `x1`: __ B02 __
* Processor 2's `x1`: __ B03 __
> * B02 = ?
> * B03 = ?
---
## Problem `C`
Since having full bypassing can be very costly, we attempt to reorder the instructions in this loop so that we can minimize the total number of cycles per loop iteration while using a single bypass path.
```cpp
loop:
slli a4, a3,5
or a5, a0, a7
xor a3, a4, a2
add a1, a2, a3
sub a6, a5, a2
blt a6, a2, loop
```
We can change the order of the instructions in the program as long as it does not change the final result. In what order would you execute the 6 instructions in the loop so that you only need a single bypass path?
1. Here, we select `EXE` $\to$ `DEC` bypass path. Please list the opcodes in order of execution: __ C01 __ (split in comma)
> * C01 = ?
2. Now, suppose we are offered another processor. This processor is identical to the processor used above with full bypassing, except that it can make branch decisions in the decode stage rather than the execute stage. The disadvantage is that this increases the clock period from `400` ps (before) to `450` ps (with the branch calculated in decode).
* Which processor is faster (old: branch decision in `EXE` and t~CLK~ = 400ps, new: branch decision in `DEC` and t~CLK~ = 450ps)? __ C02 __
> * C02 = ?
---
## Problem `D`
Consider the following C code:
```cpp
int price[6] = {7, 5, 8, 10, 15, 7};
int maximum = 10, c = 3, t = 5;
for (int i = 0; i < 6; i++) {
if (price[i] > maximum)
maximum = price[i];
}
int total_cost = maximum + c + t;
```
Then, the translated RISC-V assembly:
```cpp
// x4 = 0x24 - length of price in bytes
// x5 = 0x3 - c
// x6 = 0x5 - t
// x7 = 0xA - maximum
// x1 = 0x400 - address of price[0]
start: addi x2, x0, 0
slli x2, x2, 2
loop: add x8, x2, x1
lw x3, 0(x8)
bge x7, x3, skip
mv x7, x3
ori x7, x7, 0
skip: addi x2, x2, 4
blt x2, x4, loop
add x7, x7, x5
add x7, x7, x6
```
Assume the registers are initialized to the values specified in the assembly code comments.
In the following five-stage pipelined RISC-V processor (`IF`, `DEC`, `EXE`, `MEM`, `WB`):
* All branches are predicted not-taken. (Always fetch from `PC + 4`).
* Branch decisions are made in the `EXE` stage.
* The pipeline has full bypassing.
* The processor annuls instructions following taken branches.
* Assume that in the first iteration of the loop both branches are taken.
1. How many cycles did it take to execute the first loop iteration on this processor? Make sure not to include the first two instructions at label start in your cycle count.
* Cycles to execute first iteration of the loop on this processor: __ D01 __
> * D01 = ?
2. If you could modify your fetch stage to always fetch the correct next instruction instead of predicting all branches not taken, how many cycles will it now take to execute the first iteration of the loop on this modified processor? __ D02 __
> * D02 = ?
3. Now, let's change this processor **without** bypassing. That is, all data hazards are resolved by stalling. How many cycles did it take to execute the first loop on this processor? __ D03 __
> * D03 = ?
---
## Problem `E`
Given the standard RISC-V datapath, determine if the following is implementable or not without any additional functional units? Assume the instruction is not a pseudoinstruction encoding.
1. Consider the new instruction `isnull rd, rs1` which check if an input given through `rs1` is considered `NULL` or not by C standard. The result is returned through `rd` as a bit. Is it Implementable? __ E01 __ (Answer with `Yes` or `No`)
> * E01 = ?
2. What changes would you need to make in order for the instruction to be able to execute correctly? Assume all modifications and additions are done on top of the existing single cycle datapath. Select all that apply. __ E02 __ (Anwser in the following items and use comma to split)
* `a`. Modify Branch Comparator logic.
* `b`. Modify the control signals to the `ALU`.
* `c`. Modify the control logic for the Branch Comparator.
* `d`. Modify `ALU` buses.
* `e`. Modify the control logic for `WBSel`.
* `f`. Add additional control signals for the writeback mux.
* `g`. Modify control logic for `ALU`/`ALUSel`.
* `h`. Modify the control logic for parsing `instr[31:0]`.
* `i`. Add an additional comparator.
* `j`. None of the above.
> * E02 = ?
3. `isnull rd, rs1` is not in a standard RISC-V instruction format; as we are attempting to reduce the number of hardware changes in our datapath. We instead choose to implement our instruction as a pseudoinstruction in the following format. Which of the following statements is true? Assume earlier changes propagate. Select all that apply __ E03 __ (Anwser in the items and use comma to split)
* `a`. We need to provide a second argument `x0` when calling the instruction and modify the control signals.
* `b`. We need to provide a second argument `x0` as a comparator for all branch comparisons.
* `c`. It is impossible to represent as an R-Type instruction
* `d`. We need to wire `x0` as a comparator for all branch comparisons.
* `e`. We need to wire `x0` as `rs2` and modify the control signals.
> * E03 = ?
4. We plan to add a new R-Type signed compare instruction called `comp`, into the RISC-V single-cycle datapath, to compare `R[rs1]` and `R[rs2]` and set `R[rd]` appropriately. The RTL for it is shown below.
```cpp
// comp rd, rs1, rs2
if R[rs1] > R[rs2]: R[rd] = 1
elif R[rs1] == R[rs2]: R[rd] = 0
else: do nothing
```
We want to change the datapath to make this work. We start by adding two more inputs (`0x00000000` and `0x00000001`) to the rightmost `WBSel` MUX. What else is required to make this instruction work? Select all that apply __ E04 __ (Anwser in the items and use comma to split)
* `a`. Modify Branch Comp
* `b`. Modify Imm. Gen.
* `c`. Modify the `ALU` and `ALUSel` control signals
* `d`. Modify the control logic for `RegWEn`
* `e`. Modify the control logic for `MemWEn`
> * E04 = ?
---
## Problem `F`
Much of the assembly code she writes involves iterating through arrays of integers. Instead of using several instructions to calculate the address of the next element, we propose a new instruction, `iarrn rd, rs1, rs2`, which places into rd the address of the `rs2`-th element of the array pointed to by `rs1`. This instruction does not do bounds checking and it assumes the size of an integer is 4B (32 bits). Do not assume this instruction belongs to a specific type.
In verilog, the instruction is described as follows:
```cpp
R[rd] = R[rs1] + (4 * R[rs2])
```
1. We are interested in modifying our RISC-V datapath to support this instruction. Assume we have introduced a new control bit `IArrN` which is `1` when the current instruction is `iarrn` and `0` otherwise. Using the datapath below, fill in the following table with the rest of the control bits for this instruction. If the control bit can be set to `*`, please draw an `X` in the table below.
| IArrN | PCSel | RegWEn | MemRW | WBSel | BrUn | ALUSel |
|-|-|-|-|-|-|-|
| 1 | F01 | F02 | F03 | F04 | F05 | ADD |
> * F01 = ?
> * F02 = ?
> * F03 = ?
> * F04 = ?
> * F05 = ?
2. This instruction involves changing a few hardware pieces on the datapath in addition to changing control bits above. We propose modifying the `ASel` and `BSel` muxes, and their associated control bits (circled below).
How should we change `BSel` to allow our new instruction, and all other RISC-V instructions, to execute correctly? Select one __ F06 __ Assume our `ALU`, `RegFile`, and memory units remain unchanged internally.
> * F06 = ?
3. Following the previous quetion, how should we change `ASel` to allow our new instruction, and all other RISC-V instructions, to execute correctly? Select one __ F07 __
> * F07 = ?
---
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