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tags: computer-arch
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# Quiz4 of Computer Architecture (2021 Fall)
:::info
:information_source: General Information
* You are allowed to read **[lecture materials](http://wiki.csie.ncku.edu.tw/arch/schedule)**.
* That is, an open book exam.
* We are using the honor system during this quiz, and would like you to accept the following:
1. You will not share the quiz with anyone.
2. You will not discuss the material on the quiz with anyone until after solutions are released.
* Each answer has `10` points.
* :timer_clock: 09:10 ~ 09:35 AM on Nov 23, 2021
:::
## Problem `A`
Given the timing parameters in the table below, what are the [propagation delay](https://en.wikipedia.org/wiki/Propagation_delay) and [contamination delay](https://en.wikipedia.org/wiki/Contamination_delay) of this circuit?
(DO NOT include units in your answer!)
![](https://hackmd.io/_uploads/By2ATPYOY.png)
| Gate | t~PD~ (ns) | t~CD~ (ns) |
| ---- | :--------: | :--------: |
| XOR | 2 | 1.5 |
| INV1 | 1.5 | 1 |
| AND2 | 3 | 2 |
1. Propagation delay (ns) = __ A01 __
> A01 = ?
2. Contamination delay (ns): __ A02 __
> A02 = ?
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## Problem `B`
Consider the logic diagram below, which takes 4 inputs {a, b, c, d} and computes two outputs {x, y}. Using the t~PD~ information for the gate components shown in the table below, compute the t~PD~ for the circuit.
![](https://hackmd.io/_uploads/HJOU-OFOt.png)
| Gate | t~pd~ (ns) |
| ----- | :----: |
| XNOR2 | 5.5 |
| AND2 | 3.5 |
| OR2 | 2.5 |
| INV | 1.0 |
t~PD~ (ns) = __ B01 __
> * B01 = ?
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## Problem `C`
(DO NOT include units in your answer!)
Consider the sequential circuit below, which includes registers made of D flip flops, in addition to combinational logic. All registers share a common clock, which is not shown. The squares that begin with `R` denote registers. The stars that begin with `CL` denote combinational logic. The table below contains the propagation delay and contamination delay of the components.
![](https://hackmd.io/_uploads/HJ2wGYtdY.png)
| Component | t~PD~ | t~CD~ | t~SETUP~ | t~HOLD~ |
| --------- | :---: | :---: | :------: | :-----: |
| R1 | 2 ps | 1 ps | 2 ps | 1 ps |
| R2 | 2 ps | 2 ps | 1 ps | 2 ps |
| R3 | 1 ps | 1 ps | 6 ps | 1 ps |
| CL1 | 3 ps | 2 ps | N/A | N/A |
| CL2 | 2 ps | 1 ps | N/A | N/A |
1. What are the propagation (t~PD~) and contamination delays (t~CD~) of the circuit? Recall that these are measured from the rising edge of the clock to the output.
* t~PD~ (ps) = __ C01 __
> * C01 = ?
* t~CD~ (ps) = __ C02 __
> * C02 = ?
2. What is the minimum clock period we can use for this circuit to function properly?
* Minimum clock period for correct operation (ps): __ C03 __
> * C03 = ?
3. We would like to have a functioning circuit with a clock period of 5 ps. The following table shows possible replacements for each component in the circuit along with the price for the replacement. What is the lowest amount of money we need to spend to achieve this goal? Make sure that your new circuit obeys all timing constraints.
| Component | t~PD~ | t~CD~ | t~SETUP~ | t~HOLD~ | Price (USD) |
| --------- | :---: | :---: | :------: | :-----: | :---: |
| R1-New | 1 ps | 1 ps | 2 ps | 1 ps | 1.5 |
| R2-New | 2 ps | 2 ps | 1 ps | 1 ps | 2.0 |
| R3-New | 1 ps | 1 ps | 1 ps | 4 ps | 5.0 |
| CL1-New | 2 ps | 2 ps | N/A | N/A | 1.0 |
| CL2-New | 2 ps | 2 ps | N/A | N/A | 4.0 |
* Minimum money spent ($): __ C04 __
> * C04 = ?
* Name(s) of replacement(s) purchased: __ C05 __
> * C05 = ?
---
## Problem `D`
(DO NOT include units in your answer!)
In the following circuit, the registers have a clk-to-q delay of 6ns and setup times of 5ns. NOT gates have a delay of 3ns, AND and OR gates have a delay of 7ns, and the "Black Box" logic component has a delay of 9ns.
![](https://hackmd.io/_uploads/SJNjpFYOt.png)
1. What is the maximum allowable hold time of the registers? __ D01 __ (ns)
> * D01 = ?
2. What is the minimum acceptable clock period for this circuit? __ D02 __ (ns)
> * D02 = ?
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## Problem `E`
Consider the following circuit, where `A`, `B`, and `C` are inputs and `Out1` is the output:
![](https://hackmd.io/_uploads/ByTEGqYOK.png)
1. Find the simplest (least gates used) Boolean expression that represents the same logic as above.
* Notation: NOT is represented by `~`, AND by `*`, and OR by `+`. That is also the order of presence.
* In addition, please use parentheses if needed to organize your logic correctly though do not add any extra ones.
* Please add spaces between `+` and `*` but do NOT add spaces between `~` and the letter.
* In each grouping, please organize alphabetically and put groupings before single letters. Try not to add unnecessary parentheses.
> * E01 = ?
2. Consider the unsimplified circuit. Say our OR gates take 5 ns each, the AND gates take 2 ns, and the NOT gates take 1 ns. In addition, the registers have setup time 2 ns and clk-2-q 3 ns. How long is our critical path in ns? (do NOT include units of measurement in your answer!) __ E02 __
> * E02 = ?
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