HackMD
Linux term project (2023): Improve RISC-V Emulation Performance
contributed by < qwe661234 >
Environment setup
- Clone the repository
- Follow the instructions of rv32emu
Baseline: commit 3305664
The commit 3305664 is regarded as the baseline for performance evaluation and enhancements. The RISC-V instruction set compliance with RV32I, RV32M, RV32C, and privilege can be passed by the baseline. We compare the performance of the emulator with and without the computed-goto technique using the benchmark tool CoreMark and Dhrystone.
Benchmarking with CoreMark and Dhrystone
Ensure that rv32emu binary is built properly.
- Run CoreMark
- Run Dhrystone
Benchmark result
- Mircoprocessor: Core i7-8700
| Compiler | w/ computed-goto | CoreMark (Iterations/Sec) | Dhrystone (DMIPS) |
|---|---|---|---|
| clang-15 | NO | 360.3897405 | 325.0 |
| clang-15 | YES | 434.6317140 | 391.6 |
| gcc-12 | NO | 380.4077495 | 328.0 |
| gcc-12 | YES | 444.7024895 | 415.8 |
DMIPS: Dhrystone MIPS (Million Instructions per Second)
According to benchmark result, emulator has better result with computed-goto technique.
Preliminary introduction of basic block
We utilize perf for additional performance analysis and discover that a substantial amount of time is spent on decoding instructions within the rv_step function. Consequently, we import intermediate representations (IR) and the corresponding basic block to accelerate the process of instruction decoding.
- CoreMark performance analysis result with
perffor commit 3305664
A basic block consists of one or more instructions, and we efficiently manage blocks using hash tables. During the decode stage, a new block is allocated with a capacity of up to 1024 instructions. These instructions are decoded as intermediate representations (IR) and stored within the block. We continue translating instructions until the block reaches its maximum capacity or encounters a branch instruction.
In the execution stage, the emulator executes the instructions within the basic block sequentially. If the program reaches the program counter where the basic block has already been translated, we can reuse the basic block without repeatedly decoding the instructions.
The call graph below clearly illustrates that Dhrystone frequently invokes a specific function. This observation suggests a higher likelihood of reusing the basic blocks within these functions. Running the Coremark and Dhrystone benchmarks has yielded promising results, showing that importing these basic blocks significantly reduces the overhead of instruction decoding in such scenarios.
Call graph
- Dhrystone
Benchmark result
- Mircoprocessor: Core i7-8700
| Compiler | w/ computed-goto | CoreMark (Iterations/Sec) | Dhrystone (DMIPS) |
|---|---|---|---|
| clang-15 | NO | 850.4265125 | 665.2 |
| clang-15 | YES | 854.0181165 | 741.6 |
| gcc-12 | NO | 858.7766405 | 759.2 |
| gcc-12 | YES | 870.4854225 | 799.6 |
DMIPS: Dhrystone MIPS (Million Instructions per Second)
Use tail-call optimization(TCO) to lower overhead of instruction dispatching
Definition of instruction dispatching
Dispatch is the mechanism used by a high level language emulator to transfer control from the code to emulate one instruction to the next.
There are two types of techique using in rv32emu.
Switch dispatch
Each instruction is implemented by a case in the switch statement. Instruction bodies are simply the compiler-generated code for each case.
As Re: Suggestions on implementing an efficient instruction set simulator in LuaJIT2 mentioned, the control-flow graph of an interpreter with C switch-based dispatch looks like this:
Each individual instruction execution looks like this:
The drawback of switch dispatch is the compiler would get into some troubles:
- Diamond-shaped control-flow is known to be the worst-case scenario for most optimizations and for register alloction. Nested diamond-shaped control-flow is even worse.
- The compiler doesn't have enough hints to see what the fast paths and what the slow paths are. Even if you'd be able to tell it, it still sees this as a single giant control-flow graph. Anything in this loop could potentially influence anything else, so almost nothing can be hoisted or eliminated. The slow paths kill the opportunities for the fast paths and the complex instructions kill the opportunities for the simpler instructions. As a result, all instruction emulation would be trnslated to a big loop.
- The standard register allocation heuristics fail at this scale, so the compiler has trouble keeping important variables in registers.
Direct threading (computed-goto)
We can use a direct or indirect-threaded interpreter even in C, e.g. with the computed-goto. The control-flow graph of an interpreter with computed-goto looks like this:
Why is direct threading more efficient? As stated in Computed goto for efficient dispatch tables, it's faster for two reasons:
1. The switch does a bit more per iteration because of bounds checking.
The difference between direct threading and switch dispatch is the "bounds check" step of the switch. Why is it required? the compiler is forced to generate the bounds check for the switch statement to conform to the C standard. Quoting from C99:
If no converted case constant expression matches and there is no default label, no part of the switch body is executed.
Therefore, the standard forces the compiler to generate "safe" code for the switch. Safety, as usual, has cost, so the switch version ends up doing a bit more per loop iteration.
2. The effects of hardware branch prediction.
Modern CPUs have deep instruction pipelines and go to great lengths ensuring that the pipelines stay as full as possible. One thing that can ruin a pipeline's day is a branch, which is why branch predictors exist. Since a CPU can easily pre-fetch instructions from the branch's target, successful prediction can make the pre-fetched instructions valid and there is no need to fully flush the pipeline.
Since the switch statement has a single "master jump" that dispatches all opcodes, predicting its destination is quite difficult. On the other hand, the computed-goto statement is compiled into a separate jump per opcode, so given that instructions often come in pairs, it's much easier for the branch predictor to "home in" on the various jumps correctly.
Think about it this way: for each jump, the branch predictor keeps a prediction of where it will jump next. If there's a jump per opcode, this is equivalent to predicting the second opcode in an opcode pair, which actually has some chance of success from time to time. On the other hand, if there's just a single jump, the prediction is shared between all opcodes and they keep stepping on each other's toes with each iteration.
Subroutine threading with tail-call optimization
Unfortunately, despite using direct threading for dispatching, we encountered two issues. The first issue was the significant time taken to calculate the jumping address. To address this, we refered a solution from the implementation of wasm3, a webassembly interpreter that utilizes subroutine threading with tail-call optimization for instruction dispatch. Consequently, we followed their approach by separating all instruction emulations and modifying the rv_insn_t struct. This modification allowed us to directly assign the instruction emulation function to the intermediate representation (IR) by adding a new member named impl.
The second issue is that we must create a function stack frame for each instruction emulation, which TCO can handle. TCO allows any instruction in a basic block to emulate a function by using the same function stack frame, which saves the overhead of creating function stack frames.
To fulfill the tail-call optimization requirement, we need to transform the emulation loop into a recursive version. To achieve this, we introduce a variable tailcall to the rv_insn_t struct, which helps us determine if the basic block has reached its termination. Consequently, we can rewrite the emulate function as a self-recursive function, utilizing this variable.
As shown in the statsitic below, Coremark and Dhrystone benchmarks now produces faster results than it did previously.
Benchmark result
- Mircoprocessor: Core i7-8700
| Compiler | w/ TCO | CoreMark (Iterations/Sec) | Dhrystone (DMIPS) |
|---|---|---|---|
| clang-15 | NO | 944.9438388 | 841.4 |
| clang-15 | YES | 983.6298667 | 873.4 |
| gcc-12 | NO | 952.4544735 | 905.8 |
| gcc-12 | YES | 978.6633022 | 923.4 |
DMIPS: Dhrystone MIPS (Million Instructions per Second)
TODO: JIT compilation experiments
To optimize performance with JIT, it's crucial to have an adequate number of instructions in a basic block. If the block contains too few instructions, any potential benefits may be lost due to the costs of code generation and compilation. To overcome this limitation, we can consider using an EBB strategy to extend our basic block and improve performance.
Extended Basic Block(EBB)
- A collection of basic blocks
- Tail call optimizations are more effective on extended basic blocks
To implement EBB, we employ two main strategies: recursive jump translation and retroactive block chaining.
- recursive jump translation
Target addresses of jal, cj, and cjal instructions are determined after instruction decoding, allowing for recursive translation of jump target instructions into the same basic block. - retroactive block chaining
The previous block is chained to the current block after emulation using the obtained branch target during emulation.
The result of EBB
After analyzing the number of instructions in a basic block (BB) or extended basic block (EBB) while running the CoreMark benchmark, we found that the EBB strategy significantly increases the number of instructions from less than 25 to over 300.
Benchmark result of EBB
- Mircoprocessor: Core i7-8700
| Test | commit 1c11b39 | EBB | Speedup |
|---|---|---|---|
| CoreMark | 1155.174 (Iterations/Sec) | 1351.065 (Iterations/Sec) | +16.64％ |
| dhrystone | 1017 DMIPS | 1073 DMIPS | +5.5% |
Baseline JIT compiler
Our objective with the baseline JIT compiler is to integrate it seamlessly with minimal effort. The performance of this version will serve as the foundation for future optimizations.
The workflow of JIT compiler
In the case of the interpreter, we already have the necessary components, Extended Basic Block and LFU Cache, in place for managing the basic blocks. Therefore, we can proceed with adding three new components - Code Generator, Compiler, and Code Cache - without requiring any modifications to the existing interpreter architecture.
What are the JIT compiler optimizes
1. Lower the emulation loop overhead and only one function call
In the case of the interpreter, each instruction requires a separate function call for emulation. However, when integrating the JIT compiler, we can reduce this to just one function call to emulate all instructions within an Extended Basic Block (EBB).
2. Immediate and register number are constant
Prior to code generation, all information of the instructions has been decoded.
3. Cache friendly
Most of the emulation functions are located near the subsequent emulation functions.
Benchmark Result
We integrate two compilers, clang and mir, for our experiments. Each of these compilers has its own advantages and disadvantages.
The clang compiler provides stronger optimization capabilities, but it incurs a significant launch time. On the other hand, the mir compiler has a shorter launch time, but its optimization is not as effective as clang.
clang
mir
