---
tags: computer-arch
---

# Lab0: Web-based RISC-V Emulators

## JSLinux

* [jslinux](https://bellard.org/jslinux/)
* select riscv64, Linux 4.15.0 (Buildroot), Console
Commands:
* `cat readme.txt`
> Follow its instructions

Commands:
* `uname -a`
> Linux riscv 4.15.0, risc64
* `cat /proc/cpuinfo`
> isa: rv64acdfimsu
* `cat /proc/meminfo`
> MemTotal: 251980 kB
* `nano hello.c`
> ```cpp
> #include <stdio.h>
> int main() { puts("hello"); }
> ```
> Ctrl-X: Exit
* `gcc -o hello hello.c`
* `./hello`

## [emulsiV](https://eseo-tech.github.io/emulsiV/)

[emulsiV](https://eseo-tech.github.io/emulsiV/) is a visual simulator for a simple RISC processor called Virgule.

Virgule is a 32-bit RISC processor core that implements a minimal subset of the RISC-V instruction set. Here, "minimal" means that Virgule accepts only the instructions that a C compiler would generate from a pure stand-alone C program.

## [rv32emu](https://github.com/sysprog21/rv32emu)

rv32emu relies on Emscripten to be compiled to WebAssembly. Thus, the target system should have the Emscripten version 3.1.51 installed.

Moreover, rv32emu leverages the tail call optimization (TCO) and we have tested the WebAssembly execution in Chrome with at least MAJOR 112 and Firefox with at least MAJOR 121 since they supports tail call feature. Thus, please check and update your browsers if necessary or install the suitable browsers before going further.

Check the hosted rv32emu [demo page](https://sysprog21.github.io/rv32emu-demo/).