A
We can detect a load hazard after we have fetched the dependent instruction, and so this is the earliest point at which we can stall. We’d like to add a MUX between
our ID and IF stages. This MUX should current instruction to a NOP if a load hazard exists. Assume we have a new control bit LoadHazard which is 1 when a load hazard is present and 0 otherwise. Where should we connect tunnels A, B, and C? Select one option for each letter.
A:
B:
C:
B
For each of the questions below, please create a valid K-stage pipeline of the given circuit. Each component in the circuit is annotated with its propagation delay. Show your pipelining contours and place large black circles (●) on the signal arrows to indicate the placement of pipeline registers. Give the latency and throughput of each design, assuming ideal registers (tPD=0, tSETUP=0). Remember that our convention is to place a pipeline register on each output.
(1) Show the maximum-throughput 1-stage pipeline.
Latency (ns): __________
Throughput (ns-1): __________
Diagram for B-1
(2) Show the maximum-throughput 2-stage pipeline using a minimal number of registers.
Latency (ns): __________
Throughput (ns-1): __________
Diagram for B-2
(3) Show the maximum-throughput pipeline using a minimal number of registers.
Latency (ns): __________
Throughput (ns-1): __________
Diagram for B-3
(4) Reimplement the slowest combinational component in the previous circuit (the one with a propagation delay of 4 ns) using two components with propagation delays of 2ns, as shown below. Show the maximum-throughput pipeline using a minimal number of registers.
Latency (ns): __________
Throughput (ns-1): __________
Diagram for B-4
Solutions
Latency (ns) | Throughput (ns-1) | |
---|---|---|
(1) | 11 | 1/11 |
(2) | 14 | 1/7 |
(3) | 12 | 1/4 |
(4) | 12 | 1/3 |