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optimize LogUp challenge in IVC

background

In pull-request read-write lookup offline-memory-checking logUp-based implementation in (Super)Nova R1CS discussion, one of remains question is to optimise the cost of random oracle circuit in IVC. This post try to address the issue and propose a design.

Design rationale

One of the nice property to derive challenge via random oracle in folding IVC is we can decouple random oracle into function composition, and relax one or more of function to loose property, e.g. one of them not nessesary to satisify indifferentiable from a random oracle, while still keep overall composition result indifferentiable from random oracle. With relaxation, we implement relaxed function in IVC step circuit, while in the final SNARK pass accumuation result to another random oracle function to get the challenge which indifferentiable from random oracle.

Random Oracle

Terminology cited from Proving the correct execution of concurrent services in zero-knowledge

Giving

H=ϕ(R(x)),

with below

  • xFn
  • R:FnF
    is collision resistent encoding

R even can be non-uniform, and not indifferentiable from a random oracle

  • ϕ:FF
    is random oracle

Then

H is random oracle

reference proof https://hackmd.io/@2DQ_BR_sTUOyIfPms3lGVw/r1TNUj8q6

collision resistent encoding function R design

In each step circuit, we know how many read/write it will have. Per read/write we need to encoding

(a,vprev,v,tprev,t) 5 field elements and accumulated with prev acc value to obtain new acc and pass to next round.

To design a collision resistent hash, and with idea from pedersen hash, we can design as below: in setup phase we can pre-generate random ordered-set field values

[f0,f1,...fn], for
f0,f2,...fnF
.

In zkVM setting, one step circuit in SuperNova might represent one opcode. Each opcode read/write are bounded. Giving max read/write num is

k,
n=5×k
.

Question:

fi need to be prime?

Giving

(a,vprev,v,tprev,t), we decompose each field value into bit decomposition and concat all as

bits = bit(
a
) || bit(
vprev
) || bit(
v
) || bit(
tprev
) || bit(
t
)

Then we can encode batched field values

(a,vprev,v,tprev,t) into an order matter single field value, assume bit concated value lead to j bits

acc=accprev+R(bits,[fi])=accprev+Σi=0jbi×fi where
bi
is the bit value of
bits
in index
i

In R1CS, This formula can be represented in just 1 R1CS constraint.

collision resistent encoding on batched read/write in a single step

To encode batched of read/write in step circuit, it's naturally viewing it as encoding vector

(a0,v0,prev,v0,t0,prev,t0,a1,v1,prev,v1,t1,prev,t1,...) from its bits representation

bits = bit(
a0
) || bit(
v0,prev
) || bit(
v0
) || bit(
t0,prev
) || bit(
t0
) || bit(
a1
) || bit(
v1,prev
) || bit(
v1
) || bit(
t1,prev
) || bit(
t1
) ||

Notice with these design, it retain the order matters feature, such that if we exchange any 2 field value from vector it lead to different encoding field value.

So the length of pre-generated constant random field set

[fi] need to cover max bits length in step circuit.

collision resistent encoding order matters across steps

For encoded acc value we can passed it to next step to aggregate to next acc value. However we need to account for one order matters scenario.

Giving vector folding step m

(vm,0,vm,1,...)

and step n = m+1

(vn,0,vn,1,...)

Then

acc=accprev+R(bitsm,[fi])+R(bitsn,[fi])

When a unhonest prover exchange 2 field value in different step yet same position, e.g.

vm,1 with
vn,1
, then the new acc value will remain unchanged, imply function R is not collision resistent with order matter.

To address this issue, we introduce step variable into accumulation formula as

acc=accprev×c+R(bits,[fi])

where

cF represent current
cth
folding step in Nova, and
c
starting from 1.

Another alternative design is

accprevc, to raise
accprev
to power
c

R collision resistent analysis

Below we will infer the probability for such collision exist

define

  • prime field
    F
    with
    p
    bits prime
  • n!=1×2×3...×n
  • m < n,
    (m,n)!=m×(m+1)×(m+2)...×n
  • l
    is max bit length of read/write absortion
  • [fi]
    is the pseudorandom generated fields set,
    fiF,il
  • N
    is total number of folding steps

base case
l
=2

To prove R is collision resistent, firstly we analyze

l = 2 case, and
[f1,f2]
field set

Then it's equivalent to find

kiF,ki>0, such that
k1×f1+k2×f2=0k1=neg(k2×f2)×f11

Giving Encoding function R

acc=accprev×c+R(bits,[fi]),c[1..N]

And define set

S={(m,N)! | m[1...N]}, subset
SS

Let

k=aiS,SSai

Subset

S got
2N
choices, each can derived respective
k
. So there are
2N
possible
k
.

It implies for

k2 we have
2N
choice, after
k2
settle down,
k1
so got
2N
choice.

The probability for

k1,k2 overlapping (collision) is

2N+2N2p

For example, giving folding steps

N=210.
p
is 255 bit. Then the probability for collision exist
211255

General case
l
> 2

For

l > 2, it is equivalent to find
k>0
, such that
k1×f1+k2×f2+k3×f3+...+kl×fl=0

We can rewrite as

k1=neg(k2×f2+k3×f3+...+kl×fl)×f11

Combination of

k2,k3,k4,...,kl lead to

2(l1)×N

choice.

Similarly,

k1 also got
2N
choice

And the probability for collision exist is

2N+2(l1)×N2p

other notes

Speical notice above analysis just prove the probability of collision exist. We still need to search solition space and verify to find it. To verify a candidate, we need to do efficient factorial decomposition, means given

k, find
b1,b2,b3,...bN[0,1]
such that

k=iNbii!

naive bruce-force search take

O(2N) time complexity, not sure is there any efficient other algorithm .

Cost analysis for R function in step circuit

Giving example

  • address
    a
    max 32 bits, accounting for 4G address
  • value
    v
    max 64 bits.
  • max read-write ts across folding is 32 bits.
  • max folding step is 64 bits

Then in R1CS

name Decomposition into Bits collision resistent R
#R1CS constraints 32 + 1 from address a
64 + 1 from value v
32 + 1 from ts
33 + 65 x 2 + 33 x 2 = 229.
giving k reads/writes
overall cost 229 x k
1
#R1CS vars 32 from address a bit
64 from value v bits
32 from ts bits
32 + 64 x 2 + 32 x 2 = 224
Giving k reads/writes, overall cost 224 x k
1

So the overall challenge cost are growing linear with number of read/write in step circuit, while still remain agnostic to table size |T|

random oracle in final SNARK

We can choose any random oracle candidate

ϕ e.g. poseidon hash in final SNARK.

The final challenge (r,

γ)

r=ϕ(final_acc)=

and

γ=ϕ(r)