ECEN 676

gem5/src/arch/riscv/isa/templates/vector_mem.isa VlIndexMicroInitiateAcc
fault = initiateMemRead(xc, EA, mem_size, memAccessFlags, byte_enable);
    
  (for o3 model)
->gem5/src/cpu/o3/dyn_inst.cc DynInst::initiateMemRead
  cpu->pushRequest(...)
  
  ->gem5/src/cpu/o3/cpu.hh pushRequest
    iew.ldstQueue.pushRequest(...)
    
    ->gem5/src/cpu/o3/lsq.cc LSQ::pushRequest
      request->initiateTranslation();

      ->gem5/src/cpu/o3/lsq.cc LSQ::????::initiateTranslation()
          sendFragmentToTranslation(...)
          
        ->gem5/src/cpu/o3/lsq.cc LSQ::LSQRequest::sendFragmentToTranslation
            _port.getMMUPtr()->translateTiming(...)
          
          (TLB translation happens here)
          ->gem5/src/arch/riscv/tlb.cc
          TLB::translateTiming

pn = []
vs = []
mask = []
rs

base_i = 0

for(n in N steps) {
  pn[base] = translate(rs + vs[base])
  for(i in vs) {
      if (element == vs[base]){
          pn[i] = pn[base]
          mask[i] = 0
      }
  }
  base = first index that is 1 in mask
}

for(i in vs) {
  if (mask[i] == 1){
      pn[i] = translate(rs + vs[i])
  }
}

gem5/src/arch/riscv/isa/decoder.isa

...
0x3: VlIndexOp::vloxei32_v(
    {{ Vd_vu[vdElemIdx] = Mem_vc.as<vu>()[0]; }}, 
    {{ EA = Rs1 + Vs2_uw[vs2ElemIdx]; }},
    inst_flags=SimdIndexedLoadOp
);
...

gem5/src/arch/riscv/isa/templates/vector_mem.isa
def template VlIndexConstructor

...
microop = new %(class_name)sMicro<ElemType>(machInst, vdRegIdx, vdElemIdx, vs2RegIdx, vs2ElemIdx, elen, vlen);    
...

gem5/src/arch/riscv/isa/templates/vector_mem.isa
def template VlIndexMicroInitiateAcc

// EA = Rs1 + Vs2_uw[vs2ElemIdx]; 
fault = initiateMemRead(xc, EA, mem_size, memAccessFlags, byte_enable);

gem5/src/arch/riscv/isa/templates/vector_mem.isa
def template VlIndexMicroCompleteAcc

...
memcpy(Mem.as<uint8_t>(), pkt->getPtr<uint8_t>(), pkt->getSize());
//Vd_vu[vdElemIdx] = Mem_vc.as<vu>()[0];
%(memacc_code)s;
...