---
tags: EAGLE_01
---

# OX08B Crypto Status.

## 1. Sync Crypto ram space of DE & eagle (svn 12284, 12286) on *ram_4000.lsd.S*
**pubkey_ram** and **cryptoreg_ram**

MEMORY
{
	rom             : ORIGIN = 0x100000, LENGTH = 0x20000
	ram             : ORIGIN = 0x180000, LENGTH = 0x45C00 /*BSS_CLEAR*/
	cfwreg_ram      : ORIGIN = 0x1C5C00, LENGTH = 0x400   /*BSS_CLEAR*/
	pubkey_ram      : ORIGIN = 0x1C6000, LENGTH = 0x400   /*BSS_CLEAR*/
	isp_fb_ram      : ORIGIN = 0x1C6400, LENGTH = 0x200   /*BSS_CLEAR*/
	snr_emb_map     : ORIGIN = 0x1C6600, LENGTH = 0x200   /*BSS_CLEAR*/
	hcmd_ram        : ORIGIN = 0x1C6800, LENGTH = 0x200   /*BSS_CLEAR*/
	safe_chk_ram    : ORIGIN = 0x1C6DC0, LENGTH = 0x240   /*BSS_CLEAR*/
	ovi_emb_map     : ORIGIN = 0x1C7000, LENGTH = 0x800   /*BSS_CLEAR*/
	cryptoreg_ram   : ORIGIN = 0x1C7800, LENGTH = 0x200   /*BSS_CLEAR*/
	isp_ram         : ORIGIN = 0x1C8000, LENGTH = 0x14000 /*BSS_CLEAR*/
	hcmd_buf        : ORIGIN = 0x1dc000, LENGTH = 0x1000  /*BSS_CLEAR*/
	ram_rombss      : ORIGIN = 0x1DF000, LENGTH = 0x1000
}

---
## 2. Add struct g_crypto_ctrl on *driver_crypto.h*
crypto interface function directly set *tcryptoctrl cryptoctrl = &gcryptoctrl;*, not get address from input parameter.

crypto register link to cryptoregram space.

static t_crypto_ctrl g_crypto_ctrl = {
		.crypto = {
			.crypto_reg[0] = (t_crypto_reg*)&ld_crypto_start,
			.crypto_reg[1] = (t_crypto_reg*)((u8*)&ld_crypto_start + 0x080),
			.crypto_reg[2] = (t_crypto_reg*)((u8*)&ld_crypto_start + 0x100),
			.crypto_reg[3] = (t_crypto_reg*)((u8*)&ld_crypto_start + 0x180),
		},
		.video_crypto_cfg = &g_video_crypto_cfg,
		.edma = &g_edma,
};

---
## 3. Enable crypto irq on *drv_cpu_interrupt.com*.
**[26]:IRQ_BIT_CRYPTO0** and **[27]:IRQ_BIT_CRYPTO1**

static f_irq_nofify_process g_irqNotifyMap[CHIP_IRQ_CNT] = {
	f_irq_notify_isp,                   //[00]:IRQ_BIT_ISP_S0_0
	f_irq_notify_isp,                   //[01]:IRQ_BIT_ISP_S0_1
	f_irq_notify_isp,                   //[02]:IRQ_BIT_ISP_S0_2
	f_irq_notify_isp,                   //[03]:IRQ_BIT_ISP_S0_3
	f_irq_notify_isp,                   //[04]:IRQ_BIT_ISP_S1_0
	f_irq_notify_isp,                   //[05]:IRQ_BIT_ISP_S1_1
	f_irq_notify_isp,                   //[06]:IRQ_BIT_ISP_S1_2
	f_irq_notify_isp,                   //[07]:IRQ_BIT_ISP_S1_3
	NULL,                               //[08]:IRQ_BIT_SHA
	NULL,                               //[09]:IRQ_BIT_VM
	NULL,                               //[10]:IRQ_BIT_TPM
	NULL,                               //[11]:unused
	f_irq_notify_timer0,                //[12]:IRQ_BIT_TIMER0
	f_irq_notify_timer1,                //[13]:IRQ_BIT_TIMER1
	f_irq_notify_timer2,                //[14]:IRQ_BIT_TIMER2
	f_irq_notify_timer3,                //[15]:IRQ_BIT_TIMER3
	f_irq_notify_sccb,                  //[16]:IRQ_BIT_SCCBM0
	f_irq_notify_sccb,                  //[17]:IRQ_BIT_SCCBM1
	NULL,                               //[18]:IRQ_BIT_SCCBMS
	NULL,                               //[19]:IRQ_BIT_SPIM
	NULL,                               //[20]:IRQ_BIT_SPIS
	f_irq_notify_uart,                  //[21]:IRQ_BIT_UART
	NULL,                               //[22]:IRQ_BIT_C2T
	NULL,                               //[23]:IRQ_BIT_GPIO
	f_irq_notify_hostcmd,               //[24]:IRQ_BIT_HOSTCMD
	f_irq_notify_fcp,                   //[25]:IRQ_BIT_FCP
	f_irq_notify_crypto,                //[26]:IRQ_BIT_CRYPTO0
	f_irq_notify_crypto,                //[27]:IRQ_BIT_CRYPTO1
	drv_cpu_dma_irq_handler,            //[28]:IRQ_BIT_EDMA
	NULL,                               //[29]:IRQ_BIT_IDC
	NULL,                               //[30]:IRQ_BIT_RGBIR
	NULL,                               //[31]:unused
	f_irq_notify_isp,                   //[32]:IRQ_BIT_ISP_S2_0
	f_irq_notify_isp,                   //[33]:IRQ_BIT_ISP_S2_1
	f_irq_notify_isp,                   //[34]:IRQ_BIT_ISP_S2_2
	f_irq_notify_isp,                   //[35]:IRQ_BIT_ISP_S2_3
	f_irq_notify_isp,                   //[36]:IRQ_BIT_ISP_S3_0
	f_irq_notify_isp,                   //[37]:IRQ_BIT_ISP_S3_1
	f_irq_notify_isp,                   //[38]:IRQ_BIT_ISP_S3_2
	f_irq_notify_isp,                   //[39]:IRQ_BIT_ISP_S3_3
	NULL,                               //[40]:IRQ_BIT_DP_SOF
	NULL,                               //[41]:IRQ_BIT_DP_EOF
	NULL,                               //[42]:unused
	NULL,                               //[43]:unused
	f_irq_notify_mrx,                   //[44]:IRQ_BIT_MIPIRX0
	f_irq_notify_mrx,                   //[45]:IRQ_BIT_MIPIRX1
	f_irq_notify_mrx,                   //[46]:IRQ_BIT_MIPIRX2
	f_irq_notify_mrx,                   //[47]:IRQ_BIT_MIPIRX3
	f_irq_notify_embl,                  //[48]:IRQ_BIT_EMBL0
	f_irq_notify_embl,                  //[49]:IRQ_BIT_EMBL1
	f_irq_notify_embl,                  //[50]:IRQ_BIT_EMBL2
	f_irq_notify_embl,                  //[51]:IRQ_BIT_EMBL3
	f_irq_notify_retime,                //[52]:IRQ_BIT_RETIMING0
	f_irq_notify_retime,                //[53]:IRQ_BIT_RETIMING1
	f_irq_notify_retime,                //[54]:IRQ_BIT_RETIMING2
	f_irq_notify_retime,                //[55]:IRQ_BIT_RETIMING3
	NULL,                               //[56]:IRQ_BIT_IMGMON0
	NULL,                               //[57]:IRQ_BIT_IMGMON1
	NULL,                               //[58]:IRQ_BIT_IMGMON2
	NULL,                               //[59]:IRQ_BIT_IMGMON3
	f_irq_notify_mtx,                   //[60]:IRQ_BIT_MIPITX0
	f_irq_notify_mtx,                   //[61]:IRQ_BIT_MIPITX1
	f_irq_notify_mtx,                   //[62]:IRQ_BIT_MIPITX2
	f_irq_notify_mtx,                   //[63]:IRQ_BIT_MIPITX3
};