---
description: In this lab, we are going to talk about Finite state machines, which are sequential systems, The FSMs are a generic approach for designing sequential systems, which will make your system easier to design, debug, and understand.
---
<h1 style='border: none'><center>Hardware Description Languages Lab 8</center></h1>
<h2 style='border: none'><center>Finite State Machines</center></h2>
<h5><center>The Islamic University of Gaza<br>Engineering Faculty<br>Department of Computer Engineering</center></h5>
<h6>Author: Mohammed Nafiz ALMadhoun<span style="float:right">2021/05/06</span></h6>
---
In this lab, we are going to talk about Finite state machines, which are sequential systems, The FSMs are a generic approach for designing sequential systems, which will make your system easier to design, debug, and understand.
## Revision
In this section, we are going to talk about the types of FSMs, and revise some of the concepts in the FSMs.
### Moore State Machine
A Moore State Machine is a state machine that changes its outputs only by depending on the state register, which means changing the inputs will not change the output until the next clock.
<center>
Moore State Machine.[^1]
</center>
### Mealy State Machine
A Mealy State Machine is a state machine that changes its outputs when the inputs changes, which means two different outputs could occur in the same clock cycle (If the input is not buffered).
<center>
Mealy State Machine.[^1]
</center>
An asynchronous system (Mealy) is faster than a synchronous system (Moore) and uses less power at the cost of introducing errors, and complexity of the design.
In this course we will focus on Moore machines, note that also synthesisers will perform better when creating a synchronous system.
### State Machine Diagram
The state machine diagram is just a way of representing state machines, which will make it easier to read and interpolate.
You can use the open-source program `qfsm` to design and simulate state machines.
http://qfsm.sourceforge.net/
<center>
Moore state machine digram.
</center>
Notice that this is a Moore state machine, the outputs will be drawn in the states, and each arrow represents the transition and its condition.
## VHDL Three-process FSM Template
In this section, we will implement a Moore state machine using VHDL, we will follow a very know architecture which is creating three processes, this will make our code easier to read and understand.
### State Register Process
```vhdl=
state_reg: process (clk)
begin
if rising_edge(clk) then
if reset_bar = '0' then
present_state <= <initial_state>;
else
present_state <= next_state;
end if;
end if;
end process;
```
This process will only create a register to hold our current state.
### Output Process
```vhdl=
outputs: process (present_state)
begin
case present_state is
-- one case branch required for each state
when <state_value_1> =>
-- assignments to outputs
when <state_value_2> =>
-- assignments to outputs
when others =>
-- assignments to outputs
end case;
end process;
```
This process will convert our state code to output, notice that the process sensitivity list has only the present state and a Moore FSM the output will change only when the state changes.
### Next State Process
```vhdl=
nxt_state: process (present_state, <inputs>)
begin
case present_state is
-- one case branch required for each state
when <state_value_i> =>
if <input_condition_1> then
-- assignment to next_state
elsif <input_condition_2> then
-- assignment to next_state
else
-- assignment to next_state
end if;
when others =>
-- assign initial_state to next_state
end case;
end process;
```
Notice that this process will calculate the next state according to the current state and the outputs, thus you can find the inputs in the process sensitivity list.
### State Digram Code
```vhdl=
library ieee;
use ieee.std_logic_1164.all;
entity test is
port (
clk: in std_logic;
rst_n: in std_logic;
i: in std_logic;
o1: out std_logic;
o0: out std_logic
);
end test;
architecture behave of test is
type state_type is (state_0, state_1, state_2);
signal next_state, present_state : state_type;
begin
state_register: process (rst_n, clk)
begin
if rst_n='0' then
present_state <= state_0;
elsif rising_edge(clk) then
present_state <= next_state;
end if;
end process;
outputs: process (present_state)
begin
case present_state is
when state_0 =>
o1 <= '0';
o0 <= '0';
when state_1 =>
o1 <= '0';
o0 <= '1';
when state_2 =>
o1 <= '1';
o0 <= '0';
when others =>
o1 <= '0';
o0 <= '0';
end case;
end process;
nxt_state: process (present_state, i)
begin
case present_state is
when state_0 =>
if i = '1' then
next_state <= state_1;
else
next_state <= state_2;
end if;
when state_1 =>
if i = '1' then
next_state <= state_2;
else
next_state <= state_0;
end if;
when state_2 =>
if i = '1' then
next_state <= state_0;
else
next_state <= state_1;
end if;
when others =>
next_state <= state_0;
end case;
end process;
end behave;
```
Notice that we defined a *State* type:
```vhdl=
type state_type is (state_0, state_1, state_2);
```
## Lab Tasks
### Task 1: Sequance Detector
Design a state machine that detects the input "0111", the state machine will have one input (which is a serial input), and one output that indicates if the input occurs for one clock cycle.
Note: Start detecting the input from left to right.
### Task 2: Traffic Light
Well, this is a traditional state machine assignment, in this task, you should design a traffic light state machine which contains three lights (Green, Yellow, Red).
The state machine has 2 inputs, which indicate the following:
* `00`: Normal (Red -> Yellow -> Green -> Yellow -> Red).
* `01`: Force Red.
* `10`: Force Yellow.
* `11`: Force Green.
And three outputs (Green, Yellow, Red).
Notice that the period for Red and Green should be three times as Yellow (Which means you should repeat the states, or create a counter).
###### tags: `VHDL` `IUG`
<center>End Of Lab 8</center>
[^1]: VHDL for Engineers by Kenneth Short
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