---
description: In this lab, we are going to talk about loops, how we could implement them, and what is the benefits of having loops in an HDL, then we will talk about variables, and understand how variables got synthesized into hardware.
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<h1 style='border: none'><center>Hardware Description Languages Lab 7</center></h1>
<h2 style='border: none'><center>Loops & Variables</center></h2>
<h5><center>The Islamic University of Gaza<br>Engineering Faculty<br>Department of Computer Engineering</center></h5>
<h6>Author: Mohammed Nafiz ALMadhoun<span style="float:right">2021/04/14</span></h6>

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In this lab, we are going to talk about loops, how we could implement them, and what is the benefits of having loops in an HDL, then we will talk about variables, and understand how variables got synthesized into hardware.

## Loops

Just like regular programming, loops will iterate over a sequential code for n times, we could create an infinite loop but it will not be synthesized.

The loop could be performed on a discrete type, and will termite after n iterations, or the use of `exit` keyword.

[loop_label:] for identifier in range loop
    sequence_of_statements
end loop [loop_label];

The loop could cause the create components, and elements for each iteration, for example, you could use the loop to create multiple full adders.

So instead of repeating your hardware, you could describe the behaviour of your hardware, and the synthesizer will do the job.

Note that loops are sequential statements, so you could only use them inside a process.

### Example 1: Magnitude Comparator

library ieee;
use ieee.std_logic_1164.all;

entity magnitude_comparator is port (
    a: in std_logic_vector(3 downto 0);
    b: in std_logic_vector(3 downto 0);
    a_gt_b: out std_logic;
    a_eq_b: out std_logic;
    a_lt_b: out std_logic
);

end entity;

architecture behaviour of magnitude_comparator is
begin

    comp: process (a, b) begin
        -- Reset
        a_gt_b <= '0';
        a_eq_b <= '0';
        a_lt_b <= '0';
        for i in 3 downto 0 loop
            if (a(i) = '1' and b(i) = '0') then
                a_gt_b <= '1';
                exit;
            elsif (a(i) = '0' and b(i) = '1') then
                a_lt_b <= '1';
                exit;
            elsif i = 0 then
                a_eq_b <= '1';
            end if;
        end loop;
        
    end process;
end architecture;

To compare 4 bits, we will need to check the most significant bit first, so if we find that a is larger than b, or a is less than b, we will change the output and exit the loop, if the loop reacted zero, that means the first two conditions never become true, so a will be equal to b.

**Note:** Before the loop (at the process start), we reset all the outputs, but the signal won't change until the process got suspended.

### Example 2: Comparator Test Bench

In this example, we will use loops to test all possible values the comparator could take, notice that in the test bench you could do things that are not synthesizable.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity mc_testbench is
end entity;

architecture mc_testbench of mc_testbench is
    component magnitude_comparator port (
        a: in std_logic_vector(3 downto 0);
        b: in std_logic_vector(3 downto 0);
        a_gt_b: out std_logic;
        a_eq_b: out std_logic;
        a_lt_b: out std_logic
    );
    end component;
    
    signal a, b: std_logic_vector(3 downto 0);
    signal a_gt_b, a_eq_b, a_lt_b: std_logic;
begin 
    uut: magnitude_comparator port map (a, b, a_gt_b, a_eq_b, a_lt_b);

    process begin
        for i in 0 to 15 loop
            for j in 0 to 15 loop
                a <= std_logic_vector(to_unsigned(i, 4));
                b <= std_logic_vector(to_unsigned(j, 4));
                wait for 100 ns;
                if a > b then
                    assert a_gt_b = '1' and a_eq_b = '0' and a_lt_b='0' report "A greater than B fail!";
                elsif a < b then 
                    assert a_gt_b = '0' and a_eq_b = '0' and a_lt_b='1' report "A less than B fail!";
                else 
                    assert a_gt_b = '0' and a_eq_b = '1' and a_lt_b='0' report "A equal B fail!";
                end if;
            end loop;
        end loop;
        
        wait; -- just waiting forever!
    end process;
end architecture;

## Variables

In VHDL, we have two types of variables, normal and shared, normal variables can only be accessed from one process and are synthesizable, a shared variable can be used from multiple processes but are not synthesizable.

The variables are used inside a process, the variable will remember its value from the last execution of the process (you won't need that always), unlike singles a change to a variable will be present in the same execution cycle of the process.

### Example 1: Even Parity Generator

In this example, we will generate a single bit, this bit will make the whole data have even parity.

library ieee;
use ieee.std_logic_1164.all;

entity parity_generator is port (
    input: in std_logic_vector(31 downto 0);
    p: out std_logic
);
end entity;

architecture behavior of parity_generator is 
begin 
    p_gen: process (input) 
        variable p_temp : std_logic;
    begin
        p_temp := '0';
        for i in input'range loop
            p_temp := p_temp xor input(i);
        end loop;
        p <= p_temp;
    end process;
end architecture;

Notice that we used a variable here because a signal won't change its values inside the loop.

**TASK:** what will happen if we removed line 15?

###### tags: `VHDL` `IUG`

<center>End Of Lab 7</center>