In this lab, we are going to talk about how to define your types in VHDL, then we will solve some lab, these tasks should be solved during the Lab time.
In VHDL you could define your type, which could be a subset of a different type or a whole new type, this will be very useful in writing clean code and making things easier.
An enumeration type is defined by listing all the possible values of it, for example, we can have a type for operations:
Notice that our new type has 4 values, you could access the value by index using 'VAL
, and you could get the index of an enum using 'POS
.
Enum types are very useful and important, you will use them a lot, especially in state machines.
Please return to your textbook page 124
.
You could define a custom integer type, this type will be an integer but with a defined region.
You could define your array type (such as std_logic_vector), and define the type of each element in it.
This type is called an unconstrained array, which means that the user could choose the number of elements in it.
But you could define a constrained array
Arrays have some attributes such as:
You could also define subtype e.g:
Condier building a register file that contains 32 register, your register file has 8 inputs:
1-bit
Write Enable (W_enable)5-bit
Write Address (W_addr)32-bit
Write Data (W_data)1-bit
Read A Enable (RA_enable)5-bit
Read A Address (RA_addr)1-bit
Read B Enable (RB_enable)5-bit
Read B Address (RB_addr)and 2 outputs:
32-bit
Read A Data (RA_data)32-bit
Read B Data (RB_data)Notice that read A or B not enabled the RA_data or RB_data should be high impedance.
Design an entity that takes 8-bit unsigned input, and output three 4-bit digits, the output should be the BCD representation of the input.
examples:
VHDL
IUG