---
description: In this lab, we are going to talk about how to define your types in VHDL, then we will solve some lab, these tasks should be solved during the Lab time.
---
<h1 style='border: none'><center>Hardware Description Languages Lab 6</center></h1>
<h2 style='border: none'><center>Defining Types & Lab Tasks</center></h2>
<h5><center>The Islamic University of Gaza<br>Engineering Faculty<br>Department of Computer Engineering</center></h5>
<h6>Author: Mohammed Nafiz ALMadhoun<span style="float:right">2021/03/18</span></h6>

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In this lab, we are going to talk about how to define your types in VHDL, then we will solve some lab, these tasks should be solved during the Lab time.

## Defining Types

In VHDL you could define your type, which could be a subset of a different type or a whole new type, this will be very useful in writing clean code and making things easier.

### Enumeration Types

An enumeration type is defined by listing all the possible values of it, for example, we can have a type for operations:

library IEEE;
use IEEE.std_logic_1164.all;

entity Test is port (
    opcode: in std_logic_vector(1 downto 0)
);
end entity;

architecture Test of Test is 
    type operation_type is (summation, subtraction, multiplication, division);
    signal operation : operation_type;
begin
    operation <= operation_type'VAL(to_integer(unsigned(opcode)));
end architecture;

Notice that our new type has 4 values, you could access the value by index using `'VAL`, and you could get the index of an enum using `'POS`.

Enum types are very useful and important, you will use them a lot, especially in state machines.

Please return to your textbook page `124`.

### Integer Types

You could define a custom integer type, this type will be an integer but with a defined region.

type digit is range 0 to 9;

### Array Types

You could define your array type (such as std_logic_vector), and define the type of each element in it.

type operations_vector is array (natural range <>) of operation_type;

This type is called an unconstrained array, which means that the user could choose the number of elements in it.

But you could define a constrained array

type eight_operations is array (0 to 7) of operation_type;

Arrays have some attributes such as:
* length
* reverse_range
* range
* right
* left
* high
* low

You could also define subtype e.g:

subtype byte is std_logic_vector(7 downto 0);

## Lab Tasks

### Task 1: Register File

Condier building a register file that contains 32 register, your register file has 8 inputs:
* Clock (clk)
* `1-bit ` Write Enable (W_enable)
* `5-bit ` Write Address (W_addr)
* `32-bit` Write Data (W_data)
* `1-bit ` Read A Enable (RA_enable)
* `5-bit ` Read A Address (RA_addr)
* `1-bit ` Read B Enable (RB_enable)
* `5-bit ` Read B Address (RB_addr)

and 2 outputs:
* `32-bit` Read A Data (RA_data)
* `32-bit` Read B Data (RB_data)

Notice that read A or B not enabled the RA_data or RB_data should be high impedance.

### Task 2: Unsiged 8-bit to BCD.
Design an entity that takes 8-bit unsigned input, and output three 4-bit digits, the output should be the BCD representation of the input.

examples:

0A : 0 1 0
FF : 2 5 5
AA : 1 7 0

###### tags: `VHDL` `IUG`

<center>End Of Lab 6</center>