---
description: In this lab, we are going to learn how to create a latch, and flip-flop as an introduction to sequential logic in VHDL, but first we will learn about composite literals, and how to manipulate bit strings.
---
<h1 style='border: none'><center>Hardware Description Languages Lab 5</center></h1>
<h2 style='border: none'><center>Composite Literals & Introduction to Sequantial Logic</center></h2>
<h5><center>The Islamic University of Gaza<br>Engineering Faculty<br>Department of Computer Engineering</center></h5>
<h6>Author: Mohammed Nafiz ALMadhoun<span style="float:right">2021/03/11</span></h6>

---

In this lab, we are going to learn how to create a latch, and flip-flop as an introduction to sequential logic in VHDL, but first we will learn about composite literals, and how to manipulate bit strings.

## Composite Literals

A Composite Literals are an array of literals, but in this lab, we will focus on string literals, which we already used by using the `std_logic_vector`.

### Bit String Literals

We already learned how to assign a `std_logic_vector` value using double quotes, and it's clear that you should use `std_logic` values in that string.

architecture test of test is 
    signal m : std_logic_vector(7 downto 0);
begin 
    m <= "01010000";
end architecture;

We could also assign the value of `m` using a `hex`, `oct`, or `binary` value:

m <= H"33";

m <= O"123"; -- Notice that this value is 9-bits.

m <= B"0101_0000"; -- You could use _ between digits

### Concatenating String Literals

You could concatenate multiple string literals using the `&` symbol, this will be very useful in expanding a literal (for example, to get the carry when using numric_std).

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity adder_8bit is port (
    a : in std_logic_vector(7 downto 0);
    b : in std_logic_vector(7 downto 0);
    s : out std_logic_vector(7 downto 0);
    cout : out std_logic
);
end entity;

architecture adder_8bit of adder_8bit is 
    signal a_unsigned : unsigned (8 downto 0);
    signal b_unsigned : unsigned (8 downto 0);
    signal s_unsigned : unsigned (8 downto 0);
begin 
    a_unsigned <= unsigned ("0" & a);
    b_unsigned <= unsigned ("0" & b);
    s_unsigned <= a_unsigned + b_unsigned;
    s <= std_logic_vector(s_unsigned(7 downto 0));
    cout <= s_unsigned(8);
end architecture;

**Note:** You could select a subset of a string using range as an index.

## Sequential Logic

In this section, we are going to create some memory elements using behavioural style code, which is way easier in describing sequential logic.

### SR Latch

As you remember the SR latch will have the following truth table.

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| S | R | Q |
|:---:|:---:|:--------------:|
| 0 | 0 | Previous State |
| 0 | 1 | 0 |
| 1 | 0 | 1 |
| 1 | 1 | Invalid |

library ieee;
use ieee.std_logic_1164.all;

entity SRLatch is port (
    s, r : in std_logic;
    q, q_bar : out std_logic
);
end entity;

architecture SRLatch of SRLatch is 
    signal q_next : std_logic;
begin
    p1: process (s, r) is begin
        if (s = '1' and r = '0') then
            q_next <= '1';
        elsif (s = '0' and r = '1') then
            q_next <= '0';
        else
            q_next <= q_next;
        end if;
    end process;
    q <= q_next;
    q_bar <= not q_next;
end architecture;

Notice that we've created a signal called `q_next`, which will hold the next value of `q`, we couldn't use `q` directly because it's an output, so we couldn't read it.

### JK Flip-Flop

To create a flip-flop, we need a condition that is true only on a rising edge, we could check the two conditions `clk'event` and `clk='1'`, which mean that the clk must have an event, and its current value is `1`, so it's a rising edge.

Luckily VHDL offers functions like `rising_edge`, which could check the edge for us.

| J | K | CLK | $Q$ |
|:---:|:---:|:---:|:------:|
| 0 | 0 | ↑ | $Q_0$ |
| 0 | 1 | ↑ | 0 |
| 1 | 0 | ↑ | 1 |
| 1 | 1 | ↑ | $Q_0'$ |

Notice that the **sensitivity list** in our process only contains the clock.

library ieee;
use ieee.std_logic_1164.all;

entity JKFlipFlop is port (
    clk : in std_logic;
    j, k : in std_logic;
    q, q_bar : out std_logic
);
end entity;

architecture JKFlipFlop of JKFlipFlop is 
    signal q_next : std_logic;
begin
    p1: process (clk) is begin
        if rising_edge(clk) then
            if j = '1' and k = '0' then
                q_next <= '0';
            elsif j = '0' and k = '1' then
                q_next <= '1';
            elsif j = '1' and k = '1' then
                q_next <= not q_next;
            else
                q_next <= q_next;
            end if;
        end if;
    end process;
    q <= q_next;
    q_bar <= not q_next;
end architecture;

## Lab Tasks

### Task 1: D-Latch
You should design a D-Latch with Enable.

### Task 2: D-Flip-Flop
You should design a D-Flip-Flop, which has 3 inputs `D`, `clk`, `clear`.

Notice that the clear is an asynchronous clear.

Create a testbench for your D-Flip-Flop

### Task 3: 8 Bit data register

This should be a trivial task, you should create an 8-bit data register, it has 2 inputs `data`, and `clk`.

###### tags: `VHDL` `IUG`

<center>End Of Lab 5</center>