Hardware Description Languages Lab 2

Basic Language Constructs of VHDL

The Islamic University of Gaza
Engineering Faculty
Department of Computer Engineering

Author: Mohammed Nafiz ALMadhoun2021/02/19

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In this lab, we are going to talk about the syntax of VHDL, and learn how to write a structural description for our hardware, then we will talk about test benches and how to write a VHDL code that tests our VHDL code.

Skeleton of a VHDL Program

We will start this section by writing a small VHDL example, this example will be a half-adder using a structural description.

library ieee;
use ieee.std_logic_1164.all;

entity half_adder is 
    port (
        a, b : in std_logic;
        s, c : out std_logic
    );
end half_adder; -- this could be `end entity;``

architecture ha_arch of half_adder is
begin
    s <= a xor b;
    c <= a and b;
end ha_arch;

notice that at lines 1 & 2, we've imported the IEEE std logic package, which is the IEEE standard for describing digital logic values in VHDL.

Entity

The entity here describes what is the outer shape of our hardware, what are the inputs and outputs of this design, we give each entity a name, which will be used to create components of this entity, and we can set this entity as the top-level entity.

After declaring the entity name, we will define the ports of this entity and the direction of each port, notice that a & b has the type std_logic and the direction in.

Types

For now, you should know how to use std_logic type, which means a single bit, and could have 9 values:

• U: uninitialized. This signal hasn't been set yet.
• X: unknown. Impossible to determine this value/result.
• 0: logic 0
• 1: logic 1
• Z: High Impedance
• W: Weak signal, can't tell if it should be 0 or 1.
• L: Weak signal that should probably go to 0
• H: Weak signal that should probably go to 1
• -: Don't care.

and std_logic_vector, which is a bus (a string of bits), to define one you could write:

a : in std_logic_vector(7 downto 0)

Architecture

The architecture is the implementation of our entity, we define the architecture with a name, then assign it to an entity with the of keyword.

Note that this is a structural architecture, which will we describe the logic in it literally, please note that this code is not a programming language, so it's not executed sequentially!

Concurrent VHDL statements

In this section, we are going to talk about the concurrent VHDL statements, which are the statements we write inside the architecture body without creating a process.

Signal Assignment

The signal assignment statement will put a value in a signal.

y <= value;

Notice that we will use single quotes ' for std_logic value, and double quotes " for strings (e.g array of std_logic).

the signal assignment could have conditions using one of the following syntaxes:

When/Else Statements

y <= (a and b) when c = '0' else
     (a or b);

So the code above will assign y to a.b when c equals 0, and a+b when others.

Note that you could have multi cases after the else part.

y <= (a and b) when c = "00" else
     (a or b ) when c = "01" else
     ( not a ) when c = "10" else
     ( not b );

With/Select Statments

with c select y <= 
    (a and b) when "00",
    (a or b ) when "01",
    ( not a ) when "10",
    ( not b ) when others;

Lab Tasks

Task 1: Your first VHDL code.

In this task, you should write an entity named (my_first_entity), which has 2 inputs, and export 3 outputs, the outputs should be the and & or & xor operation between the two inputs.

Task 2: Simple Multiplexer.

In this task, you should design an entity with 3 inputs:

• a : std_logic
• b : std_logic
• selection : std_logic_vector(1 downto 0)

and 1 output:

• y : std_logic

The output should be:

• a and b when selection = "00"
• a or b when selection = "01"
• a xor b when selection = "10"
• 0 when others

tags: VHDL IUG

End Of Lab 2