Digital Design Lab 5

More Combinational Designs

The Islamic University of Gaza
Engineering Faculty
Department of Computer Engineering

Author: Mohammed Nafiz ALMadhoun2021/11/08

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Introduction

In this lab, we are going to design some common combinational devices, we will start by designing a binary magnitude comparator, then we will design a decoder and encoder.

Magnitude Comparator

We will start our magnitude comparator by comparing only two bits, our system will have two inputs (A and B), and we will have three outputs (A=B, A>B and A<B).

A	B	A = B	A > B	A < B
0	0
0	1
1	0
1	1

The problem with this device is that we couldn't extend it to compare multi-bits numbers, so we need to create a similar device but it should take the output of the previous bit comparator, so it can cascade the results.

One Bit Comparator with Cascading

And this is the internals of it:

One Bit Comparator

Note that this device is useless and slow, usually, you will find the same idea of cascading but with a bigger number of bits (e.g 8-bit comparator with cascading).

Decoder & Encoder

In this section, we will talk about very useful designs, which are decoders and encoders, as you might notice from the name, the encoder will do the opposite job of the decoder.

Decoder

The decoder is a device that takes a binary number, and outputs 1 on that number output line, in a more scientific way it converts binary information from \(n\) input lines to a maximum of \(2^n\) unique output lines.

3Bit Decoder

As you notice, we have 3 bits input, thus we will have \(2^3=8\) outputs.

Notice that the decoder should make only one output different from the others (Some decoders assign zero to the active line, and one to every other output).

The decoder internal design is very simple that we won't cover!

Note: The decoder is a very useful device, you could control the active device using a decoder, or you could implement any truth table using a decoder and OR gates.

Encoder

The encoder will take \(2^n\) inputs and encode them back to binary, notice that one of the inputs should be one and the others should be zeros.

Useless design that will do nothing!

As you notice, when we connected our decoder outputs to the encoder inputs, it just outputs the decoder inputs.

Note that this is a priority encoder, which means if two lines are one it will output the bigger number (depends on the design).

Introduction to Verilog

In this section we will talk a bit about Verilog, which is a hardware description language, this language will allow us to design our digital system without the need for drawing gates or knowing exactly the gates we will use.

The advantage of using an HDL is that you could easily send it to a manufacturer and create a single chip with your custom logic, and the tools that we will use will automatically optimize our logic for speed or fewer gates.

To start writing our Verilog code we will need to install Quartus Prime Lite Edition, which is free software that manages the process of converting Verilog code to logic gates, you can download the program for the link below:
https://fpgasoftware.intel.com/?edition=lite
Note: Install the program and MAX II, MAX V device support.

Creating Verilog Project

To create a new project, which we will need to add our code to, follow these steps:

1. File -> New Project Wizard.
2. Next -> Select project location, and write the name of the project.

Project Wizard

3. Next -> Next -> Next -> Select Device Family.

Selecting Device Family

4. Select synthesis tool and simulator.

Synthesis tool and simulator

5. Finish.

Creating a new Verilog file.

1. File -> New
2. Verilog HDL File.
3. OK

Creating new Verilog File

Write the following code in the file

// This is a 2-Bit Decoder
module Name (A, B, out_0, out_1, out_2, out_3);
	input A, B;
	output out_0, out_1, out_2, out_3;
	wire not_A, not_B;
	
	not (not_A, A);
	not (not_B, B);
	and (out_0, not_A, not_B);
	and (out_1, A, not_B);
	and (out_2, not_A, B);
	and (out_3, A, B);
endmodule

The main module name should be as the project name, the module is a device that has inputs and outputs, the explanation of each line of code is as follows:

• Line 1: This is just a comment.
• Line 2: Define our module name, and its inputs and outputs.
• Line 3: We define that we want A and B to be input.
• Line 4: We define our outputs.
• Line 5: We created two wires with the names not_A and not_B.
• Line 7: We created an inverter (the output is not_A, the input is A).
• Line 8: Same as Line 7 with different outputs and inputs.
• Line 9-12: We created four AND gates, the output is the first argument, the inputs are the second and third arguments.
• Line 13: We end the module code!

Now save your file as Name.v, and press the Start Compilation button.

Start Compliation Button

After the program finishes compiling, you could see the logic created by it from this menu.

Locate in RTL Viewer

This will open a new window, which we could see the logic gates of our design.

RTL Viewer

Hope you've enjoyed this long lab XD

Lab Tasks

Task 1: Prime numbers detector

Using a 3-bit decoder, design a circuit that will detect if the input is a prime number or not, and as you know the prime number from 0 to 7 are 2, 3, 5, 7.

Use a 74LS138 IC (3-bit decoder) and 74LS08 IC (Quad 2-Input AND Gate) to design the detector.

Note 1: Design it using Logisim before starting wiring!
Note 2: If the number is prime output 0.

Task 2: BCD Compartor

Using 74LS85 IC (4-bit comparator), you will need to design a circuit that detects if a number is above 9, you will need 4 bits as inputs from the switches, and the other 4 bits from the comparator should be constant (9).

Homework 1:

Just install Quartus and repeat the above steps, you should submit a screenshot for the RTL Viewer.

Datasheets

• 74/138 datasheet: https://www.futurlec.com/Datasheet/74ls/74LS138.pdf
• 74/08 datasheet: https://www.futurlec.com/Datasheet/74ls/74LS08.pdf
• 74/85 datasheet: https://www.futurlec.com/Datasheet/74ls/74LS85.pdf

tags: Digital Design Digital IUG Computer Engineering

End Of Lab 5