# SR Flip Flop


## Source Code

module SRFF(S,R,CLK,Q,Qbr);
	 input S,R,CLK;
	 output reg Q,Qbr;
	 
	 always @(negedge CLK)
	 begin 
	 Q = S | (Q&~R) ;
	 Qbr = R |((~Q)&(~S));
	 
	 end
	 


endmodule

## Test Fixture

module SRtest;

	// Inputs
	reg S;
	reg R;
	reg CLK;

	// Outputs
	wire Q;
	wire Qbr;

	// Instantiate the Unit Under Test (UUT)
	SRFF uut (
		.S(S), 
		.R(R), 
		.CLK(CLK), 
		.Q(Q), 
		.Qbr(Qbr)
	);

	initial begin
		// Initialize Inputs
		S = 0;
		R = 0;
		CLK = 0;

		// Wait 100 ns for global reset to finish
		#100;
		
		end
		
		always #10 CLK=~CLK;
		
		initial begin
		S=0;
		R=1;
		
	   #100;
		
	   S=0;
		R=0;
       		
	    #100;
    	
	   S=1;
		R=0;
		
        
		// Add stimulus here

	end
      
endmodule

## Simulation


# JK Flip Flop


## Source Code

module JK_FF(j,k,q,qbr,clk
    );
	 
	 input j,k,clk;
	 
	 output reg q, qbr;

	 

	 initial begin

	 q = 0;

	 qbr = 0;

	 end
	 
    always @(posedge clk)
	 begin 
	 q <= (~q&j)|(q&~k);
	 qbr <=(~q&~j)|(q&k);
	 
	 end
	 

endmodule

## Test Fixture

module JK_FF_test;

	// Inputs
	reg j;
	reg k;
	reg clk;

	// Outputs
	wire q;
	wire qbr;

	// Instantiate the Unit Under Test (UUT)
	JK_FF uut (
		.j(j), 
		.k(k), 
		.q(q), 
		.qbr(qbr), 
		.clk(clk)
	);

initial begin
		// Initialize Inputs
		j = 0;
		k = 0;
		clk = 0;

		// Wait 100 ns for global reset to finish
		#100;
		
		end
		
		always #10 clk=~clk;
		
		initial begin
		j=0;
		k=1;
		
	   #100;
		
	   j=0;
		k=0;
       		
	    #100;
    	
	   j=1;
		k=1;
		
        
		// Add stimulus here
	end
      
endmodule

## Simulation


# D Flip Flop


## Source Code

module D_FF(d,clk,q,qbr
    );
	 
	 input d,clk;
	 output reg q,qbr;
	 
	 always@(negedge clk)
	 begin
	 q=d;
	 qbr=~d;
	 end


endmodule

## Test Fixture

module D_FF_test;



	// Inputs

	reg d;

	reg clk;



	// Outputs

	wire q;

	wire qbr;



	// Instantiate the Unit Under Test (UUT)

	D_FF uut (

		.d(d), 

		.clk(clk), 

		.q(q), 

		.qbr(qbr)

	);



	initial begin

		// Initialize Inputs

		d = 0;

		clk = 0;



		// Wait 100 ns for global reset to finish

		#100;

      

		// Add stimulus here



	end

	always #10 clk=~clk;
	
	initial begin
		d=0;
		
	   #100;
	   d=1;
       		
	  end

      

endmodule

## Simulation


# T Flip Flop


## Source Code

module T_FF(t,clk,q,qbr
    );
	 
	 input t,clk;
	 output reg q,qbr;

	 

	 initial begin

	 q = 0;

	 qbr = 0;

	 end
	 
	 always@(negedge clk)
	 begin
	 q=t^q;
	 qbr=~(t^q);
	 end


endmodule

## Test Fixture

module T_FF_test;



	// Inputs

	reg t;

	reg clk;



	// Outputs

	wire q;

	wire qbr;



	// Instantiate the Unit Under Test (UUT)

	T_FF uut (

		.t(t), 

		.clk(clk), 

		.q(q), 

		.qbr(qbr)

	);



	initial begin

		// Initialize Inputs

		t = 0;

		clk = 0;



		// Wait 100 ns for global reset to finish

		#100;

        

		// Add stimulus here



	end

	always #10 clk=~clk;
	
	initial begin
		t=0;
		
	   #100;
	   t=1;	
	  end

 

endmodule

## Simulation


# 4-Bit Synchronous Up Counter

## Source Code

module UP_COUNTER (  input clk,              
                  input rstn,              
                  output reg[3:0] out);    
  always @ (posedge clk) begin
    if (! rstn)
      out <= 0;
    else 
      out <= out + 1;
  end
endmodule

## Test Fixture

module UP_COUNTER_test;

	// Inputs
	reg clk;
	reg rstn;

	// Outputs
	wire [3:0] out;

	// Instantiate the Unit Under Test (UUT)
	UP_COUNTER uut (
		.clk(clk), 
		.rstn(rstn), 
		.out(out)
	);

	always #5 clk = ~clk;
 
  // This initial block forms the stimulus of the testbench
  initial begin
    // 1. Initialize testbench variables to 0 at start of simulation
    clk <= 0;
    rstn <= 0;
 
    // 2. Drive rest of the stimulus, reset is asserted in between
    #20   rstn <= 1;                   
    #80   rstn <= 0;
    #50   rstn <= 1;
 
    // 3. Finish the stimulus after 200ns
  end
      
endmodule

## Simulation


# 4-Bit Asynchronous Down Counter


## Source Code

module DOWN_COUNTER(input clk, reset, output [3:0] counter
    );
reg [3:0] counter_down;

// down counter
always @(posedge clk or posedge reset)
begin
if(reset)
 counter_down <= 4'hf;
else
 counter_down <= counter_down - 4'd1;
end 
assign counter = counter_down;
endmodule

## Test Fixture

module DOWN_COUNTER_test;

	// Inputs
	reg clk;
	reg reset;

	// Outputs
	wire [3:0] counter;

	// Instantiate the Unit Under Test (UUT)
	DOWN_COUNTER uut (
		.clk(clk), 
		.reset(reset), 
		.counter(counter)
	);

	initial begin 
clk=0;
forever #5 clk=~clk;
end
initial begin
reset=1;
#20;
reset=0;
end
      
endmodule

## Simulation