# Ripple Carry Adder

## Source Code

module RCA(a1,a2,a3,a4,b1,b2,b3,b4,cin,s1,s2,s3,s4,cout);
	input a1,a2,a3,a4,b1,b2,b3,b4,cin;
	output s1,s2,s3,s4,cout;
	wire c1,c2,c3;
	
	FullAdder A (
    .a(a1), 
    .b(b1), 
    .c(cin), 
    .sum(s1), 
    .carry(c1)
    );
	 FullAdder B (
    .a(a2), 
    .b(b2), 
    .c(c1), 
    .sum(s2), 
    .carry(c2)
    );
	 FullAdder C (
    .a(a3), 
    .b(b3), 
    .c(c2), 
    .sum(s3), 
    .carry(c3)
    );
	 FullAdder D (
    .a(a4), 
    .b(b4), 
    .c(c3), 
    .sum(s4), 
    .carry(cout)
    );
endmodule

## Test Fixture

module RCA_Test;

	// Inputs
	reg a1;
	reg a2;
	reg a3;
	reg a4;
	reg b1;
	reg b2;
	reg b3;
	reg b4;
	reg cin;

	// Outputs
	wire s1;
	wire s2;
	wire s3;
	wire s4;
	wire cout;

	// Instantiate the Unit Under Test (UUT)
	RCA uut (
		.a1(a1), 
		.a2(a2), 
		.a3(a3), 
		.a4(a4), 
		.b1(b1), 
		.b2(b2), 
		.b3(b3), 
		.b4(b4), 
		.cin(cin), 
		.s1(s1), 
		.s2(s2), 
		.s3(s3), 
		.s4(s4), 
		.cout(cout)
	);

	initial begin
		// Initialize Inputs
		a1 = 0;
		a2 = 0;
		a3 = 1;
		a4 = 1;
		b1 = 0;
		b2 = 0;
		b3 = 1;
		b4 = 0;
		cin = 0;

		#100;
		
		a1 = 1;
		a2 = 1;
		a3 = 1;
		a4 = 1;
		b1 = 1;
		b2 = 1;
		b3 = 1;
		b4 = 1;
		cin = 0;

		#100;
        
		// Add stimulus here

	end
      
endmodule

## Simulation


# Binary Coded Decimal

## Source Code

module BCD(a1,a2,a3,a4,b1,b2,b3,b4,cin,s1,s2,s3,s4,cout);

	input a1,a2,a3,a4,b1,b2,b3,b4,cin;
	output s1,s2,s3,s4,cout;
	wire c1,c2,c3,c4, temp1, temp2;

	RCA A (
    .a1(a1), 
    .a2(a2), 
    .a3(a3), 
    .a4(a4), 
    .b1(b1), 
    .b2(b2), 
    .b3(b3), 
    .b4(b4), 
    .cin(cin), 
    .s1(c1), 
    .s2(c2), 
    .s3(c3), 
    .s4(c4), 
    .cout(temp2)
    );
	 
	 assign temp1=((c4&c3)|(c4&c2)|temp2);
	 
	 RCA B (
    .a1(c1), 
    .a2(c2), 
    .a3(c3), 
    .a4(c4), 
    .b1(0), 
    .b2(temp1), 
    .b3(temp1), 
    .b4(0), 
    .cin(0), 
    .s1(s1), 
    .s2(s2), 
    .s3(s3), 
    .s4(s4), 
    .cout(cout)
    );

endmodule

## Test Fixture

module BCD_Test;

	// Inputs
	reg a1;
	reg a2;
	reg a3;
	reg a4;
	reg b1;
	reg b2;
	reg b3;
	reg b4;
	reg cin;

	// Outputs
	wire s1;
	wire s2;
	wire s3;
	wire s4;
	wire cout;

	// Instantiate the Unit Under Test (UUT)
	BCD uut (
		.a1(a1), 
		.a2(a2), 
		.a3(a3), 
		.a4(a4), 
		.b1(b1), 
		.b2(b2), 
		.b3(b3), 
		.b4(b4), 
		.cin(cin), 
		.s1(s1), 
		.s2(s2), 
		.s3(s3), 
		.s4(s4), 
		.cout(cout)
	);

	initial begin
		// Initialize Inputs
		a1 = 0;
		a2 = 0;
		a3 = 0;
		a4 = 0;
		b1 = 1;
		b2 = 1;
		b3 = 1;
		b4 = 1;
		cin = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
      
endmodule

## Simulation


# Carry Loop Adder

## Source Code

module CLA(a0,a1,a2,a3,b0,b1,b2,b3,cin,s1,s2,s3,s4);
	input a0,a1,a2,a3,b0,b1,b2,b3,cin;
	output s1,s2,s3,s4;
	wire g0,g1,g2,g3,p0,p1,p2,p3,c1,c2,c3,c4,temp1,temp2,temp3,temp4;

	assign g0 = a0&b0;
	assign p0 = a0^b0;
	assign c1 = cin&p0+g0;
	FullAdder A (
    .a(a0), 
    .b(b0), 
    .c(c1), 
    .sum(s1), 
    .carry(temp1)
    );
	 
	assign g1 = a1&b1;
	assign p1 = a1^b1;
	assign c2 = c1&p1+g1;
	FullAdder B (
    .a(a1), 
    .b(b1), 
    .c(c2), 
    .sum(s2), 
    .carry(temp2)
    );
	 
	assign g2 = a2&b2;
	assign p2 = a2^b2;
	assign c3 = c2&p2+g2;
	FullAdder C (
    .a(a2), 
    .b(b2), 
    .c(c3), 
    .sum(s3), 
    .carry(temp3)
    );
	 
	assign g3 = a3&b3;
	assign p3 = a3^b3;
	assign c4 = c3&p3+g3;
	FullAdder D(
    .a(a2), 
    .b(b3), 
    .c(c4), 
    .sum(s4), 
    .carry(temp4)
    );


endmodule

## Test Fixture

module CLA_Test;

	// Inputs
	reg a0;
	reg a1;
	reg a2;
	reg a3;
	reg b0;
	reg b1;
	reg b2;
	reg b3;
	reg cin;

	// Outputs
	wire s1;
	wire s2;
	wire s3;
	wire s4;

	// Instantiate the Unit Under Test (UUT)
	CLA uut (
		.a0(a0), 
		.a1(a1), 
		.a2(a2), 
		.a3(a3), 
		.b0(b0), 
		.b1(b1), 
		.b2(b2), 
		.b3(b3), 
		.cin(cin), 
		.s1(s1), 
		.s2(s2), 
		.s3(s3), 
		.s4(s4)
	);

	initial begin
		// Initialize Inputs
		a0 = 0;
		a1 = 0;
		a2 = 0;
		a3 = 0;
		b0 = 1;
		b1 = 1;
		b2 = 1;
		b3 = 1;
		cin = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
      
endmodule

## Simulation


# 4-Bit Comparator

## Source Code

module Comparator(
    );
	 
	input [3:0] a,b;
	output aeqb,agtb,altb;
	reg aeqb,agtb,altb;

	always @(a or b)
	begin
	aeqb=0; agtb=0; altb=0;
	if(a==b)
	aeqb=1;
	else if (a>b)
	agtb=1;
	else
	altb=1;
end


endmodule

## RTL

## Test Fixture

module comparator_test;

	// Inputs
	reg [3:0] a;
	reg [3:0] b;

	// Outputs
	wire aeqb;
	wire agtb;
	wire altb;

	// Instantiate the Unit Under Test (UUT)
	Comparator uut (
		.a(a), 
		.b(b), 
		.aeqb(aeqb), 
		.agtb(agtb), 
		.altb(altb)
	);

	initial begin
		// Initialize Inputs
		a = 4'b0000;
		b = 4'b0001;

		// Wait 100 ns for global reset to finish
		#100;
      a = 4'b0011;
		b = 4'b0010;
		
		#100;
      a = 4'b0001;
		b = 4'b0101;
		
		#100;
      a = 4'b0011;
		b = 4'b0011;
		// Add stimulus here

	end
      
endmodule

## Simulation