Organization contact [name= K. Desnos (kdesnos at insa-rennes.fr)] Mailing list: You can subscribe to a dedicated mailing-list, that will exclusively be used to send seminar and Ph.D. defense announcements. To subscribe, send an e-mail to email@example.com with the following subject line (with YOUR first and last names): subscribe vaader-seminars FirstName LastName Next Seminars 31.03.2023 - 14:00 INSA Build. 10, Room 229 & Zoom3/15/2023
by Luc Le Magoarou (IETR SIGNAL) - 2023.04.27 source: https://www.youtube.com/watch?v=uHGlCi9jOWY&ab_channel=BabaBrinkman Abstract Wireless communication systems constantly evolve towards more sophistication in order to meet ever-growing efficiency requirements. This evolution entails more complex data processing, which can be handled via classical signal processing techniques or the more recent machine learning approaches. Signal processing tends to be computationally efficient but can rely on simplistic analytic models, while machine learning is data-adaptive by nature but requires heavy computations to be trained. Could we take the best of both worlds by designing computationally efficient AI methods built on models usually used in signal processing?3/2/2023
by Pedro Ciambra (UniCamp & IETR VAADER) - 2023.04.11 Abstract Existing dataflow tools are difficult to integrate with the state-of-the-art industrial compilers. We approach this problem by creating an IR for static dataflow using MLIR, a flexible and powerful framework for modular compilers, and demonstrate it by implementing a novel dead code elimination optimization that relies on both actor and graph information.3/2/2023
by Ophélie Renaud (IETR - VAADER) - 2023.03.01 Video Abstract This paper introduces a fast method to generate high performance parallelized code from a dataflow specification of an application. Dataflow Models of Computation (MoCs) are efficient programming paradigms for expressing the parallelism of an application. Traditionally, mapping and scheduling methods for dataflow MoCs rely on complex graph's transformations to explicit their parallelism which can result in complex graph for embarrassingly parallel applications. For such applications, state-of-the-art mapping and scheduling techniques are prohibitively complex, while the exposed parallelism often exceeds the parallel processing capabilities of the target architecture. We propose SCAPE, an automated method to control the complexity of the pre-scheduling graph transformation by using information from the architecture and application models. By decreasing the complexity of the graph, the mapping scheduling task is accelerated at the potential expense of the produced schedule. Our method offers a limited and controlled decrease of the schedule quality while enabling mapping and scheduling execution time between 1 and 2 orders of magnitude faster than state-of-the-art techniques.3/1/2023
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