Assignment1: RISC-V Assembly and Instruction Pipeline

contributed by < handsomehsia >

make an isoceles triangle

Step 1 - Take number of rows to be printed, n.
Step 2 - Make an iteration for n times
Step 3 - Print " " (space) for in decreasing order from 1 to n-1
Step 4 - Print "* " (start, space) in increasing order
Step 5 - Return

C code

#include <stdio.h>
int main()
{
    int i, j, size = 8;
    for (i = 1; i < size + 1; i++)
    { // 印出第i列
        for (j = 1; j < size + i; j++)
        { // 每一列有size+i-1個符號
            if (j < size - i + 1)
            { // 在size-i左邊(含)的符號是空白
                printf(" ");
            }
            else
            { // 其他的是*
                printf("*");
            }
        }
        printf("\n");
    }
    return 0;
}

Result

Assembly code

info
cycles	1812
retired	1186
CPI	1.53
IPC	0.65

.data
length: .word 8  #legs size
star:  .string "*"
spa:  .string " "
newline:  .string "\n"
.text 
#s2 = i
#s3 = j
#s4 = legs size
#t0,t1,t2 = temp size

main:	
	add s2, x0, x0        # i =0
	add s3, x0, x0        # j = 0
	lw  s4, length        # size = 8
loop1:
	la a0, newline        #print newline
	li a7, 4
	ecall

	addi	s2, s2, 1		   #i = i+1
	addi	t0, s4, 1		   #t0 = size+1
	blt   s2, t0, cond    #for(i < size+1)
	j exit		
			 
loop2:
	addi s3, s3, 1	      #j = j+1
	add t2, s4, s2	      #t0=size+i

	bge   s3, t2, loop1   #for(j < size+i )
	sub  t1, s4, s2	      #t1=size-i
	addi t1, t1, 1        #t1=size-i+1
	blt  s3, t1, printSpace	   #if (j < size - i+1)				
        j printStar	

cond:
	add s3, x0, x0        # init j
	j loop2

printStar:
	la a0, star
	li a7, 4
	ecall
	j loop2	

printSpace:		
	la a0, spa
	li a7, 4
	ecall
	j loop2

exit:
    	li a7, 10
    	ecall 

Pipeline

Pipeline has 5 stages, IF, ID, EX, MEM and WB. We use pipeline to improve the efficiency of program.

use add x18 x0 x0 funtion for example

• IF (Instruction Fetch)

  • Fetch the instruction from the Instruction Memory.
  • It's depends on the PC (program counter) which is a register can record the address of the instruction being executed at the current time.
  • PC will be change if some instructions happen like beq, jal, j etc.

  -ex. pc send pc addr to instruction memory and fetch the instruction addr out 0x00000933
  

• ID (Instruction Decode)

  • Registers fetch and instruction decode.
  • It also has some control signals which can decide the register behavior. like write data, clear bit etc.
    -ex.We fetch 0x0000093 out from instruction memory last time,and now we decode 0x0000093 by its type and there is four part of the result
    
    
    

• EX (Execution)

  • This stage will execute the instruction according to the opcode.
  • In branch instruction will check the result is true/false to set the flag and change the PC.
  • ex.ALU will calculate 0x00000000 + 0x00000000 = 0x00000000 to initialize x18 to zero value.
    
    
    

• MEM (Mem structure)

  • Write/Read data with the data memory.
  • It's decide the address of the memory according to opcode.
  • It has two signals MemRead and MemWrite which can distinguish between write and read operation.
  • ex.Add instruction don’t need to access memory or write data. It just need to pass by the mem stage.
    
    

• WB (Write Back)

  • Write ALU output back to the register file.
  • it has a signal MemtoReg which decide whether write data back to the register file.

Description