contribute by < JinYu1225 >
Introduction
The objective of this assignment is to develop a single-cycle RISC-V CPU, named MyCPU, using Chisel, a hardware description language based on Scala. The process involves forking and modifying code from ca2023-lab3 to complete the CPU construction. The final step is to execute the project developed in Assignment2 on the MyCPU.
The complete project can be accessed here
For further details on Chisel, Scala, and CPU construction as part of this assignment, refer to Lab3: Construct a single-cycle RISC-V CPU with Chisel.
Hello World in Chisel