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描述電路的三種層次
tags:
verilog
digital design
邏輯設計
邏設
English Version
English Version
Structure Description ( Structural Modeling )
Format:
Gate Level Description
Example:
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Learn More →Dataflow Description ( Dataflow Modeling )
Format:
又稱為
continuous assignment
.只要
=
右邊的值改變,assgin statement 就會執行一次=
左邊只能是 wire輸出 “ 不 ” 可以包含輸入。例如:
assign a = a + b;
一個參數只能被 assign 一次。例如:
assign a = b; assign a = c; //error
assign 的值也可以用大括弧來串聯 bit。
assign a = { 1'b0, 1'b1 }; // a = 2'b01
assign a = { 2{2'b10} }; // a = 4'b1010
其他更詳盡的語法說明,請參考 Lexical Conventions。
Behavior Description ( Behavior Modeling )
格式
Behavior 也稱作 procedural assignment,意思是會依照一些程序條件來觸發。
又稱作 block assignment
可分成兩種,initial block 和 always block。
initial block:只會在程式一進來的時候執行一次,但是 initial block 是不能夠合成的,只能用在testbench。
always block:只要 sensitivity list 裡的 value 有改變,就會執行一次 always block 裡面的程式。
往往 sensitivity list 內的參數會過多,為避免少寫,通常會用 * 代替。
在這個範例中,always block 裡面使用的是 blocking assignment,也就是在這個 block 內部會依序執行,之後在 sequential circuit 的時候會再詳細的介紹。
更多詳盡的說明,請同學 google 尋找,或上 「Verilog HDL 教學講義」。
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Learn More →- The image file may be corrupted
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Learn More →