Lab 1 Basic Verilog

tags: verilog digital design

• Lab 1 Basic Verilog
  • Work Flow
  • Circuts
  • An Example
  • Question 1 Gate Level Description Practice
  • Question 2 Dataflow Description Practice
  • Question 3 Behavior Description Practice
  • Question 4 K-Map Implementation
  • Question 5 K-Map Implementation 2 (Don't care condition)
  • Question 6 Multiple Outputs
  • How to Run Your Code
  • Lab Rules

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Work Flow

You can find the templates and testbench on ILMS !!!

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Circuts

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An Example

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Question 1 Gate Level Description Practice

Please implement the fig(2) using Gate Level Description.

module lab1_1 (a, b, c, out);

    intput a, b, c;
    output out;
    
    // Please implement you design here
    // only Gate Level Description is allowed.

endmodule

You can find the template on ILMS.

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Question 2 Dataflow Description Practice

Please implement the fig(2) using Dataflow Description.

module lab1_2 (a, b, c, out);

    intput a, b, c;
    output out;
    
    // Please implement you design here
    // only Dataflow Description is allowed.

endmodule

You can find the template on ILMS.

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Question 3 Behavior Description Practice

Please implement the fig(2) using Behavior Description.

module lab1_3 (a, b, c, out);

    intput a, b, c;
    output out;
    
    // Please implement you design here
    // only Behavior Description is allowed.

endmodule

You can find the template on ILMS.

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Question 4 K-Map Implementation

$$F(w,x,y,z)=\sum (0,1,2,4,5,6,8,9,12,13,14)$$

1. Please draw the K-map in your report.
2. Please implement
   $out=F(w,x,y,z)$ using Dataflow Description.

module lab1_4 (w, x, y, z, out);

    intput w,x,y,z;
    output out;
    
    // Please implement you design here
    // only Dataflow Description is allowed.
    
    // Hints: the code may look like...    
    // assign out = (a&b) ... | (a&c) ... ;

endmodule

You can find the template on ILMS.

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Question 5 K-Map Implementation 2 (Don't care condition)

$$F(w,x,y,z)=\sum (1,3,7,11,15)$$

$$d(w,x,y,z)=\sum (0,2,5)$$

1. Please draw the K-map in your report.
2. Please implement
   $out=F(w,x,y,z)+d(w,x,y,z)$ using Dataflow Description.

module lab1_5 (w, x, y, z, out);

    intput w,x,y,z;
    output out;
    
    // Please implement you design here
    // only Dataflow Description is allowed.
    
    // Hints: the code may look like...    
    // assign out = (a&b) ... | (a&c) ... ;

endmodule

You can find the template on ILMS.

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Question 6 Multiple Outputs

You can use one of the descriptions we mentioned before to answer this question.

p.s. You don't need to simplfy the following circuit. :)))

out_0 = (a + b') c' (c + d)
out_1 = (c'd + bcd + cd')(a' + b)
out_2 = (ab + c) d + b'c 

module lab1_6 (a, b, c, d, out_0, out_1, out_2);

    input a, b, c, d;
    output out_0, out_1, out_2;
    
    // Please implement you design here
    
    // Hints: 
    // assign out_0 = .... ;
    // assign out_1 = .... ;
    // assign out_2 = .... ;

endmodule

You can find the template on ILMS.

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How to Run Your Code

1. To Run the code. Please login to the server and enter a server node (ic21 ~ ic27) first.

2. Upload your codes and testbenchs.

3. Run the command:

ncverilog lab1_[QuestionID]_tb.v lab1_[QuestionID].v


ex.

ncverilog lab1_1_tb.v lab1_1.v

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Lab Rules

1. Deadline: 4/13

2. Submit your code to ILMS. Please upload the questions separately. Do not zip them.

3. The file content tree should look like:

   • lab1_1.v
   • lab1_2.v
   • lab1_3.v
   • lab1_4.v
   • lab1_5.v
   • lab1_6.v
   • lab1_StudentID.pdf (ex. lab1_105066666.pdf)

4. Your report should contains two K-maps(Q4, Q5) and some feedbacks.

   • Up to 2 pages (one for K-maps, and the other one for suggestions)
   • feedbacks can be:
     • What do you learn in Lab1
     • Do you have any suggestion on the course or lab.
     • or something you want to talk to us.