Synthesis Flow

tags: Digital IC Design

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design compiler 的指令使用的是 tcl 語言,有興趣的可以先去看一下

Brief introduce to synthesis flow

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Detail of synthesis flow

1. 準備 HDL code

​​​​    synthesizable code

2. Specify Libraries

設定於 .synopsys_dc.setup 這個 file 中(前面的句點代表這個檔案是隱藏檔)

  • Symbol library : 提供 design compiler 具有 symbol view 的功能
  • Synthetic library: 即 design ware library。在初始化 DC 時,會自動 include DesignWare library 中的 standard.sldb,這個 library 用於實現 verilog 描述的運算子(例如 +, -, *, / ),先轉換至性能較差的電路。若要性能比較好的電路,我們再額外填入 dw_foundation.sldb , DC 再幫我們替代

    結論 : Synthetic library is for optimization purposes

  • link library : 設計中不可避免的要用到一些合作廠商的 hard IP,這些IP並不是 designer 設計的而是直接例化( instantiation )使用。在合成的過程中並不希望 DC 把這些模型轉換為 standard cell,所以就需要用到 link library,link library 就是告訴 DC 這些 IP 不用你合成,直接調用 link Library 的 lib 即可
  • target library : 即 technology library,由 ASIC vendor 提供(台積電、聯電)。在合成的最後一步,將先前的 GTECH library mapping 成 target library。

    DC 就是根據 target library 中給出的 delay 資訊來計算 path delay

3. Read Design

analyze -f verilog $DESIGN\.v elaborate $DESIGN current_design $DESIGN

讀檔後, design compiler 會檢查 RTL code 是否有誤,所以可以在 terminal 上觀察是否有 LATCH

4. Setting Design Environment

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Design environment
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Script of design compiler
  • Operating Conditions : 模擬 PVT( Process, Voltage, Temperature ) 改變後對電路的影響

製程提供了三種情況 best case( fast )、typical case、worst case( slow ),一般 worst case 必須為最先考慮的

  • Wire Load Model : 預測線路之間的 RC 效應

    net delay 是根據 wire load model 所決定

  • System Interface : 模擬自己的 design 與其他外部的關係
    • set_drive : drive characteristics for input ports.
    • set_fanout_load : fanout loads on output ports.
    • set_load : loads on input and output ports.
    • set_driving_cell : 外部的驅動電路

5. Setting Design Constraints

  • Design Rule Constraints
  • Design Optimization constraints ( 使用者自定義 speed, area )

Design Rule Constraints

  1. set_max_capacitance : 定義 output pin 可以驅動的最大負載電容
  2. set_max_transition : 定義轉態時間的最大容忍值
  3. set_fanout_load, set_max_fanout : 直接看例子

Input pins have fanout_load attribute( load they place on driving nets )
Output pins have max_fanout attribute( max load they can drive )

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​​​​注意: max_fanout( 7 ) 必須大於或等於 total fanout load ( 1.0 + 3.0 + 2.0 = 6 ) ,
​​​​如果沒辦法達成就得依靠 buffer 幫助提高 driving 能力或者替代成更強的 driving cell, 
​​​​max_fanout constraint 就可以設更大

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set_ideal_network : 因為有些情況下 transition time or capacitance 必須 assign 0,可以透過這個 command 設定。例如 clock 訊號,一般在合成時不會處理,等到 APR 才做 clock tree synthesis

Design Optimization constraints

  • create_clock : 設定電路的 clock period
  • set_clock_latency
    • clock source latency: clk source 到 clk definition point
    • clock network latency: clk definition point 到 FF 的 clock pin

    latency(延遲) : 處理 1 個 operation 需要花的時間
    throughput(吞吐量) : 單位時間內可以執行幾次 operation

    舉例: 一間農場專門製造牛奶,製造一罐牛奶需要3小時,整個生產線一天可以製造80罐。 latency 則為 3 小時, throughput 為1天80罐

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Clock latency Clock jilter
  • set_clock_jitter : 與真實事件的理想時間的誤差,通常是受到訊號干擾,如 crosstalk等(synthesis 沒有這個指令,通常會加到 clock_uncertainty內)

  • set_clock_uncertainty : 解決 Pre-CTS前的 clock skew

    • clock skew : 電路中有些 FF 與 clock source 距離比較近,有些則比較遠。但 net 上都會有一些的電阻存在,導致每顆 FF 收到的 clock 訊號都有些許的誤差,我們稱這個誤差為 clock skew
      (Pre-CTS: uncertainty = margin + skew)
      (Post-CTS: uncertainty = margin )
  • set_input_delay / set_output_delay:模擬 前一級/後一級 別人的 IP

set t_in Tclk2q + Tc1 set_input_delay $t_in -clock clk [all_inputs]
set t_out Tsetup + Tc2 set_output_delay $t_out -clock clk [all_outputs]
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Condition of input delay
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Condition of ouput delay

set_max_delay:如果電路中沒有 clock signal 使用此 command( 純組合電路 )
set_fix_hold:跟 DC 說請幫忙修復 hold time violation。但通常不在合成做這件事

6. Select Compile Strategy

  • Top-down Compile : 把 top module design 與 submodule 攤開來,一併合成,對 DC 來說可以一次看到所有的 design ,最後出來的 performance 會比較棒。但這跟做法比較耗時
  • Bottom-up Compile : 從子電路開始合成,一路到 Top module
  • Mixed Compile : 手動指定哪塊電路要 Top-down 還是 Buttom-up

7. Optimize the design
這一步要開始 compile,轉換 RTL code 至 netlist. 在 compile之前,由於我們在寫電路的時候,常常會在 module 內部 call 很多次 submodule,所以我們要先解決 multiple instance的問題。DC 內建提供了三種方式來解決:

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Multiple instance of cell

multiple instance of a design reference

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uniquify set_dont_touch ungroup
  • uniquify:每個 submodule 獨立出來

    這個方法需要更多 compile 的時間

  • set_dont_touch {U2/U3 U2/U4}: 同個 submodule 只 compile 一次,之後有相同的 submodule 直接 reference
  • ungroup {U3 U4}:直接把 submodule 打散

    performance 最好,但它是這三種方法中最耗時、最吃記憶體)

  • compile : Default sythesis algorithm.
  • compile_ultra : 有點像 ungroup 在做的事,把電路的 hierarchy 打散。所以這種方法當然 performance 更好,但更吃記憶體與耗時

8. Analyze

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report area report timing
  • report_area:

    • Total cell area : 所有 cell 的面積
    • Total area:net area + total cell area

      在合成階段還未實際繞線,net area 則是透過 wire load model 初估而成(非常不准),所以一般我們合成完只看 total cell area

  • report_timing : check slack 是不是 non-negative(MET)

    “slack” = 電路所需時間 (required time) 減實際到達時間 (arrival time)

    design compiler default 只會顯示一條 critical path ( 最花時間的 path )

9. Save Design

  • gate level verilog file(.v):儲存 gate level netlist

  • standard delay format(.sdf):記載 線路/cell 的 delay

  • synopsys deisgn constraint(.sdc): APR 需要知道我們在 design compiler 中都打了什麼 delay constraint

    前面有說 synthesis = translate + optimization + mapping,可以想想 translate/optimization/mapping 分別對應到什麼 command

Reference Image

[1~2] https://www.eng.auburn.edu/~nelson/courses/elec5250_6250/slides/LogicSynthesis.pdf
[3] https://blogs.cuit.columbia.edu/zp2130/clock_tree_latency_skew_uncertainty/
[4] https://pro.focusrite.com/what-is-jetpll
[5~8] https://slideplayer.com/slide/3478219/

[待補]

  1. set_multicycle_path