# TESTBED
###### tags: `Digital IC Design`

### <font color="blue"> Timescale</font>

// Syntax
`timescale <time_unit>/<time_precision>

| timescale | Delay | Time Delay |
| ------------------ | ------ | ---------- |
| timescale 10ns/1ns | #5 | 50ns |
| timescale 10ns/1ns | #5.738 | 57ns |
| timescale 10ns/10ns| #5.5 | 60ns |
| timescale 10ns/100ps | #5.738 | 57.4ns |

> 因為 simulator 的 timing 資訊會根據 top file 的 timescale

### <font color="blue"> Dunp Waveform of .fsdb </font>
$fsdbDumpfile(“filename”);
$fsdbDumpvars(0, test_module_name, “+mda”);
> [詳細內容觀看別的網站](https://blog.eetop.cn/blog-1518355-433686.html)

### <font color="blue"> Including Timing Information </font>
$sdf_annotate("sdf file", instance name);
> [詳細內容觀看別的網站](https://blog.eetop.cn/blog-1518355-433686.html)

### <font color="blue"> Port Connection </font>
跟 [Instantiation](https://hackmd.io/@derek8955/BkK2Nb5Jo/https%3A%2F%2Fhackmd.io%2FDUc5Ud-4Sg-OmIbTjeavOw) 一樣的方式

### <font color="blue"> Example </font>

`timescale 1ns/100ps // time_unit = 1ns, time_precision = 100ps

`include "PATTERN.v"

`ifdef RTL
    `include "DESIGN.v"
`elsif GATE
    `include "DESIGN_SYN.v"
`endif

module TESTBED;
    wire clk, rst_n, data_in, data_out;

// dump waveform
initial begin
	`ifdef RTL
            $fsdbDumpfile("DESIGN.fsdb");
            $fsdbDumpvars(0,"+mda");
	`elsif GATE
            $fsdbDumpfile("DESIGN_SYN.fsdb");
            $sdf_annotate("DESIGN.sdf",U_DESIGN); // including timing information
            $fsdbDumpvars(0,"+mda");
	`endif
end

// port connection    
DESIGN U_DESIGN
(
	// Input signals
	.clk(clk),
	.rst_n(rst_n),
    .data_in(data_in),
	// Output signals
    .data_out(data_out),
);


PATTERN U_PATTERN
(
	// Input signals
	.clk(clk),
	.rst_n(rst_n),
    .data_in(data_in),
	// Output signals
    .data_out(data_out),
);  
    
endmodule