Static Timing Analysis(STA)
回到主頁面
What is STA
- STA 是一個驗證 timing 是否有 violation 的方法,透過檢查電路中所有 path 的 Timing 是否符合 constraint 的要求
- DTA( Dynamic Timing Analysis ) 是另外一種驗證方法,利用測試資料對整個電路跑 simulation
DTA 因為要對所有電路跑過一次邏輯模擬,相對速度不會比 STA 快。而且 STA 可以確保所有的 Timining path 有被 detect
Goal of STA
- 檢查 synthesis 之後 timing 是否有 violation ( Logic synthesis )
- 檢查 scan chain insertion 之後 timing 是否有 violation ( DFT )
- 檢查 Place & Route 之後 timing 是否有 violation ( APR )
Timing Path
在數位電路中有四條 Timing path:
- in2reg (Path1) : input to register
- reg2reg (Path2) : register to register
- reg2out (Path3) : register to output
- in2out (Path4) : input to output ( 盡量避免這條路徑 )
Image Not Showing
Possible Reasons
- The image file may be corrupted
- The server hosting the image is unavailable
- The image path is incorrect
- The image format is not supported
Learn More →
|
Ref : [1] |
Term definition
- setup time : 輸入訊號必須在 clock edge 之前 tsu 即穩定
- hold time : 輸入訊號必須在 clock edge 之後 thd 都保持穩定
- contamination delay(tcd) : 輸入訊號改變之後 Y 開始改變的時間
- propagation delay(tpd) : 輸入訊號改變之後 Y 改變至穩定的時間
Image Not Showing
Possible Reasons
- The image file may be corrupted
- The server hosting the image is unavailable
- The image path is incorrect
- The image format is not supported
Learn More →
|
Image Not Showing
Possible Reasons
- The image file may be corrupted
- The server hosting the image is unavailable
- The image path is incorrect
- The image format is not supported
Learn More →
|
setup time & hold time |
contamination delay & propagation delay |
Ref : [2] |
Ref : [3] |
- Clock-to-Q contamination delay : clock edge 到 Y 開始改變的時間
- Clock-to-Q propagation delay : clock edge 到 Y 改變至穩定的時間
Image Not Showing
Possible Reasons
- The image file may be corrupted
- The server hosting the image is unavailable
- The image path is incorrect
- The image format is not supported
Learn More →
|
Clock-to-Q contamination/propogation delay |
Ref : [4] |
Setup Time Criterion & Hold Time Criterion
Image Not Showing
Possible Reasons
- The image file may be corrupted
- The server hosting the image is unavailable
- The image path is incorrect
- The image format is not supported
Learn More →
|
Image Not Showing
Possible Reasons
- The image file may be corrupted
- The server hosting the image is unavailable
- The image path is incorrect
- The image format is not supported
Learn More →
|
Ref : [5] |
Setup Time Criterion |
Image Not Showing
Possible Reasons
- The image file may be corrupted
- The server hosting the image is unavailable
- The image path is incorrect
- The image format is not supported
Learn More →
|
Image Not Showing
Possible Reasons
- The image file may be corrupted
- The server hosting the image is unavailable
- The image path is incorrect
- The image format is not supported
Learn More →
|
Ref : [5] |
Hold Time Criterion |
Timing Violation
設計 IC 必須權衡 Performance & Power & Area,但在這些事之前必須先解決 Timing 問題,確保所有的 Timing path 都不可有 Timing violation。否則可能導致 Function Fail
Timing Violation 分成以下兩種:
- Setup Time Violation : 一個 cycle 內太多件事要做,可以設計 pipeline 或是調高 clock period
Input delay( 見 synthesis flow ) 不適當也會造成 setup time violation
- Hold Time Violation : 代表 delay 不足,可以在 violate path
hold time 若有 violation,一般在 clock tree synthesis 之後才改善
Reference Image
[1] https://www.synopsys.com/glossary/what-is-static-timing-analysis.html
[2] http://www.vlsi-expert.com/2011/04/static-timing-analysis-sta-basic-part3a.html
[3] https://www.sciencedirect.com/topics/computer-science/contamination-delay
[4] https://slideplayer.com/slide/17358331/
[5] https://medium.com/mirkat-x-blog/iclab-lab04-note-6a19d03b8d42
Apendix –- 為何 flip-flop 需在 clock edge 的前後保留一段準備時間
https://www.edn.com/understanding-the-basics-of-setup-and-hold-time/
Apendix –- youtube介紹影片
https://www.youtube.com/watch?v=xCA54Qu4WtQ&list=PLpCkjM331Aa8JNoZ1s1o1txve2wlf9pCP
Apendix –- Clock ga