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The efabless Caravel project–-Chip design for the software-oriented - Tim Edwards, Mohamed Shalan

tags: COSCUP2021 Skilled en COSCUP2021 Bringing Open Source Software to Hardware TR313

歡迎來到 https://hackmd.io/@coscup/2021 共筆

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Slido: https://app.sli.do/event/uq1d7voh

Hardware 的困難：

  1. require EE degree
  2. cycle time
  3. cost

Open Source EDA -> 需要封閉的 PDK

Skywater water-pdk => SKY130 data

成果

caravel picoRV32 搭配 closed source chips
EDA tool: OpenLane

10 mm^2 的 user project space
可以插入 user chip 跟 picoRV32 搭配

OpenLane

RTL to GDSII open source tool

Synthesis

verilog/VHDL + Standard cell library (SCL) => gate

Floor and Power Planning

大致決定各部件的擺放位置
Power metal structure

Place

Place gates

  • Global place -> 大致位置
  • Detail place -> aligned one grid

Clock Tree Synthesis (CTS)

H tree or X tree 確保 clock 信號在 chip 都同步

Routing

佈線，將 gate 用 Metal 線連起來

Signoff

DRC + LVS

+       +

 \____/

OpenLane 希望達到一鍵完成上面所有步驟

Caravel all done in open source tool:

Slack group for skywater PDK

裡面是參加eFabless專案的Slack，可以在裡面問任何想問的問題。
https://invite.skywater.tools/

Select a repo