(待補)The Introduction of Intel Ethernet IP Cores

撰寫日期：2020/12/25

作者: 正昇

由於目前開發上多應用Intel的平台，因此分享一下之前沒碰過的 PHY 與 MAC IP 設計

Intel 10 Gbps Ethernet PHY

特色

1. Full Duplex 全雙工
2. 64b/66b encoding/decoding 支援64B/66B編碼格式
3. Clock Oscillator

• ATX PLL : 12.5Gbps~17.4Gbps。
• fPLL：1Gbps~12.5Gbps
• CMU PLL ：Lower than 10 Gbps

3. Ethernet PHY Module
4. PCS (Physical Coding Sublayer)
5. PMA (Physical Medium Attachment)
6. Optional

• FEC (Forward Error Correction , FEC)**

Intel Low-Latency 10 Gbps MAC

1. Low-Latency and Full-duplex in 10Gbps data rate
2. Flow Control
3. CRC-32 Computation and Insertion
4. Programmable IPG (Inter Packet Gap)
5. Programmable maximum length
6. Basic, VLAN, Stacked VLAN Support
7. Frame monitoring and statistics
8. Support IEEE 1588v2 PTP
9. Operating Frequency 312.5 MHz, 156.25MHz

MAC TX Data Path

1. XGMII Encapsulation
2. CRC-32, Address, Padding Bytes Insertion
3. Inter-Packet Gap Generation and Insertion
4. XGMII Transmission

MAC RX Data Path

1. XGMII Decapsulation
2. Checking CRC
3. Optional Address, Frame Type, Length Checking
4. CRC and Padding Bytes Removal

Flow Control

1. IEEE 802.3 Flow Control
2. Priority-based Flow Control

IEEE 1588v2 PTP Features

1. PTP is a protocol that accurately synchronizes all real time-of-day clocks in a network to a master clock.
2. 1-step and 2-step clock sync
3. Support PTP event and general messages
4. Time of Day (ToD) Clock Generator IP

• 64-bit timestamp is for transparent clock devices
• 96-bit timestamp is for ordinary clock and boundary clock devices.

1. IEEE 802.3, UDP/IPv4 Packet Support