---
title: 系統晶片 -RV32I
tags: 系統晶片
---
[TOC]

---

# understanding of verilog(Chinese)
- [hackmd link](https://hackmd.io/vBVr9ZUPSziCN3gXF4TpUw)
# Final HW-System chip implementation
- [hackmd link](https://hackmd.io/@cindyrumi/chipInplement)
# My design
- decode mode

- instruction set
## 5 stage draft design
- 實作的部分都是依照下方草稿的命名方式
1. 
2. 
3. 
4. 
5. 

## instruction
### I-type

opcode [5:0] //[6~0] 
rd  [4:0] //[11~7]
func3  [3:0] //[14~12]
rs1  [4:0] //[19~15]
mm[11:0]  [11:0] //[31~20]

## ori