• understanding of verilog(Chinese)
• Final HW-System chip implementation
• My design
  • 5 stage draft design
  • instruction
    • I-type
  • ori

---

understanding of verilog(Chinese)

• hackmd link

Final HW-System chip implementation

• hackmd link

My design

• decode mode
  

  

• instruction set
  

  

5 stage draft design

• 實作的部分都是依照下方草稿的命名方式

1. 
2. 
3. 
4. 
5. 

instruction

I-type

opcode [5:0] //[6~0] 
rd  [4:0] //[11~7]
func3  [3:0] //[14~12]
rs1  [4:0] //[19~15]
mm[11:0]  [11:0] //[31~20]

ori