TP 2 & 3 - HackMD

:::info **Nom**: Hoang Nguyen VU, Zhenming WANG **TP numéro**: 2 & 3 ::: # TP 2 & 3 ## Afficheur 7 segments ```vhdl library ieee; use ieee.std_logic_1164.all; entity septsegment is port ( valeur: in std_logic_vector(3 downto 0); CA, CB, CC, CD, CE, CF, CG, DP: out std_logic; AN0: out std_logic); end entity septsegment; architecture flot of septsegment is begin CA <= (not(valeur(3)) and not(valeur(2)) and not(valeur(1))) or (not(valeur(3)) and not(valeur(1)) and not(valeur(0))); CB <= (not(valeur(3) or valeur(2) or valeur(1) or valeur(0))) or (valeur(2) and not(valeur(1)) and valeur(0)) or (valeur(2) and valeur(1) and not(valeur(0))); CC <= (not( valeur(3) or valeur(2) or valeur(0))); CD <= (not(valeur(3) or valeur(2) or valeur(1))) or (not(valeur(3) or valeur(1) or valeur(0))) or (valeur(2) and valeur(1) and valeur(0)); CE <= (not(valeur(3) or valeur(1))) or (not(valeur(3)) and valeur(0)) or (not (valeur(1)) and valeur(0)); CF <= (not(valeur(3) or valeur(2))) or (valeur(1) and valeur(0)); CG <= (not(valeur(3) or valeur(2) or valeur(1))) or (valeur(2) and valeur(1) and valeur(0)); AN0 <= '0'; DP <= '1'; end architecture flot; ``` ```vhdl library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity TestSegment is end TestSegment; architecture bench of TestSegment is signal valeur: std_logic_vector (3 downto 0); signal CA, CB, CC, CD, CE, CF, CG, DP: std_logic; signal AN0 : std_logic; begin test: entity work.septsegment(flot) port map (valeur => valeur, CA => CA, CB => CB, CC => CC, CD => CD, CE => CE, CF => CF, CG => CG, DP => DP, AN0 => AN0); valeur <= "0011", "0110" after 10ns, "0100" after 20ns; end architecture bench; ``` ```xdc set_property PACKAGE_PIN T10 [get_ports CA] set_property IOSTANDARD LVCM0S33 [get_ports CA] set_property PACKAGE_PIN R10 [get_ports CB] set_property IOSTANDARD LVCM0S33 [get_ports CB] set_property PACKAGE_PIN K16 [get_ports CC] set_property IOSTANDARD LVCM0S33 [get_ports CC] set_property PACKAGE_PIN K13 [get_ports CD] set_property IOSTANDARD LVCM0S33 [get_ports CD] set_property PACKAGE_PIN P15 [get_ports CE] set_property IOSTANDARD LVCM0S33 [get_ports CE] set_property PACKAGE_PIN T11 [get_ports CF] set_property IOSTANDARD LVCM0S33 [get_ports CF] set_property PACKAGE_PIN L18 [get_ports CG] set_property IOSTANDARD LVCM0S33 [get_ports CG] set_property PACKAGE_PIN H15 [get_ports DP] set_property IOSTANDARD LVCM0S33 [get_ports DP] set_property PACKAGE_PIN J15 [get_ports valeur[0]] set_property IOSTANDARD LVCM0S33 [get_ports valeur[0]] set_property PACKAGE_PIN L16 [get_ports valeur[1]] set_property IOSTANDARD LVCM0S33 [get_ports valeur[1]] set_property PACKAGE_PIN M13 [get_ports valeur[2]] set_property IOSTANDARD LVCM0S33 [get_ports valeur[2]] set_property PACKAGE_PIN R15 [get_ports valeur[3]] set_property IOSTANDARD LVCM0S33 [get_ports valeur[3]] set_property PACKAGE_PIN J17 [get_ports AN0] set_property IOSTANDARD LVCM0S33 [get_ports AN0] ``` ## Addition ```vhdl library ieee; use ieee.std_logic_1164.all; entity add1 is port( a,b,cin : in std_logic; s,cout : out std_logic); end entity add1; architecture flot of add1 is begin s<= a xor b xor cin; cout<= (a and b) or (a and cin) or (b and cin); end architecture flot; ``` ```vhdl library ieee; use ieee.std_logic_1164.all; entity add4 IS port (a,b : in std_logic_vector(3 downto 0); cin : in std_logic; s : out std_logic_vector(3 downto 0); cout : out std_logic); end entity add4; ARCHITECTURE struct OF add4 IS signal c : std_logic_vector(4 downto 0); BEGIN c(0) <= cin; cout <= c(4); instance : for i in 0 to 3 generate add1_i : entity work.add1(flot) port map (a=>a(i),b=>b(i),cin=>c(i),s=>s(i),cout=>c(i+1)); end generate; END ARCHITECTURE struct; ``` ```vhdl library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity TestAdditionneur is end TestAdditionneur; architecture bench of TestAdditionneur is signal a,b : in std_logic_vector(3 downto 0); signal cin : in std_logic; signal s : out std_logic_vector(3 downto 0); signal cout : out std_logic; begin test: entity work.add4_generate(struct) port map (a => a, b => b, cin => cin, s => s, cout => cout); a <= "0010", "0011" after 20ns, "0101" after 30ns; a <= "0100", "0110" after 10ns, "0111" after 30ns; end architecture bench; ``` ```vhdl library ieee; use ieee.std_logic_1164.all; entity AfficheAdd4 is port(a,b : in std_logic_vector(3 downto 0); cin : in std_logic; CA, CB, CC, CD, CE, CF, CG, DP: out std_logic; AN0: out std_logic); end entity AfficheAdd4; architecture struct of AfficheAdd4 is signal cin, cout : STD_LOGIC; signal uni : STD_LOGIC_VECTOR(3 downto 0); begin cin <= '0'; add: entity work.add4_generate(struct) port map (a => a, b => b, cin => cin, s => uni, cout => cout); affiche: entity work.septsegment(flot) port map(CA => CA, CB => CB, CC => CC, CD => CD, CE => CE, CF => CF, CG => CG, DP => DP, AN0 => AN0, valeur => uni); end architecture struct; ``` ```xdc set_property PACKAGE_PIN T10 [get_ports CA] set_property IOSTANDARD LVCM0S33 [get_ports CA] set_property PACKAGE_PIN R10 [get_ports CB] set_property IOSTANDARD LVCM0S33 [get_ports CB] set_property PACKAGE_PIN K16 [get_ports CC] set_property IOSTANDARD LVCM0S33 [get_ports CC] set_property PACKAGE_PIN K13 [get_ports CD] set_property IOSTANDARD LVCM0S33 [get_ports CD] set_property PACKAGE_PIN P15 [get_ports CE] set_property IOSTANDARD LVCM0S33 [get_ports CE] set_property PACKAGE_PIN T11 [get_ports CF] set_property IOSTANDARD LVCM0S33 [get_ports CF] set_property PACKAGE_PIN L18 [get_ports CG] set_property IOSTANDARD LVCM0S33 [get_ports CG] set_property PACKAGE_PIN H15 [get_ports DP] set_property IOSTANDARD LVCM0S33 [get_ports DP] set_property PACKAGE_PIN J15 [get_ports valeur[0]] set_property IOSTANDARD LVCM0S33 [get_ports valeur[0]] set_property PACKAGE_PIN L16 [get_ports valeur[1]] set_property IOSTANDARD LVCM0S33 [get_ports valeur[1]] set_property PACKAGE_PIN M13 [get_ports valeur[2]] set_property IOSTANDARD LVCM0S33 [get_ports valeur[2]] set_property PACKAGE_PIN R15 [get_ports valeur[3]] set_property IOSTANDARD LVCM0S33 [get_ports valeur[3]] set_property PACKAGE_PIN J17 [get_ports AN0] set_property IOSTANDARD LVCM0S33 [get_ports AN0] ``` ## Soustraction ![](https://i.imgur.com/SV0Lh4q.png) ```vhdl library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity complementun is port( add_sous: in STD_LOGIC; B: in STD_LOGIC_VECTOR (3 downto 0); B_final: out STD_LOGIC_VECTOR (3 downto 0) ); end entity complementun; architecture flot of complementun is begin instance: for i in 0 to 3 generate B_final(i) <= add_sous xor B(i); end generate; end architecture flot; ``` ```vhdl library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity additionneur_soustracteur is port( add_sous : in STD_LOGIC; A,B: in STD_LOGIC_VECTOR (3 downto 0); R: out STD_LOGIC_VECTOR (3 downto 0) ); end entity additionneur_soustracteur; architecture struct of additionneur_soustracteur is signal B_final: STD_LOGIC_VECTOR (3 downto 0); begin comp_un: entity work.complementun(flot) port map (add_sous => add_sous, B => B, B_final => B_final); R<= A + B_final when add_sous = '0' else A + B_final + 1; end architecture struct; ``` ```vhdl library ieee; use ieee.std_logic_1164.all; entity AfficheAddSous is port(a,b : in std_logic_vector(3 downto 0); add_sous: in std_logic; CA, CB, CC, CD, CE, CF, CG, DP: out std_logic; AN0: out std_logic); end entity AfficheAddSous; architecture struct of AfficheAddSous is signal r,valeur: STD_LOGIC_VECTOR(3 downto 0); begin add: entity work.additionneur_soustracteur(struct) port map (A => a, B => b, R => r, add_sous => add_sous); valeur <= r; affiche: entity work.septsegment(flot) port map(CA => CA, CB => CB, CC => CC, CD => CD, CE => CE, CF => CF, CG => CG, DP => DP, AN0 => AN0, valeur => valeur); end architecture struct; ``` ```vhdl library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity TestBench is end TestBench; architecture bench of TestBench is signal A,B,R: STD_LOGIC_VECTOR (3 downto 0); signal add_sous: STD_LOGIC; begin test_bench: entity work.additionneur_soustracteur(struct) port map (add_sous => add_sous, A => A, B => B, R => R); A <= "0001", "0010" after 10ns, "0101" after 20ns, "1000" after 30ns; B <= "0001", "0110" after 20ns, "0010" after 30ns; add_sous <= '0', '1' after 15ns; end architecture bench; ``` ```xdc set_property PACKAGE_PIN T10 [get_ports CA] set_property IOSTANDARD LVCM0S33 [get_ports CA] set_property PACKAGE_PIN R10 [get_ports CB] set_property IOSTANDARD LVCM0S33 [get_ports CB] set_property PACKAGE_PIN K16 [get_ports CC] set_property IOSTANDARD LVCM0S33 [get_ports CC] set_property PACKAGE_PIN K13 [get_ports CD] set_property IOSTANDARD LVCM0S33 [get_ports CD] set_property PACKAGE_PIN P15 [get_ports CE] set_property IOSTANDARD LVCM0S33 [get_ports CE] set_property PACKAGE_PIN T11 [get_ports CF] set_property IOSTANDARD LVCM0S33 [get_ports CF] set_property PACKAGE_PIN L18 [get_ports CG] set_property IOSTANDARD LVCM0S33 [get_ports CG] set_property PACKAGE_PIN H15 [get_ports DP] set_property IOSTANDARD LVCM0S33 [get_ports DP] set_property PACKAGE_PIN J15 [get_ports a[0]] set_property IOSTANDARD LVCM0S33 [get_ports a[0]] set_property PACKAGE_PIN L16 [get_ports a[1]] set_property IOSTANDARD LVCM0S33 [get_ports a[1]] set_property PACKAGE_PIN M13 [get_ports a[2]] set_property IOSTANDARD LVCM0S33 [get_ports a[2]] set_property PACKAGE_PIN R15 [get_ports a[3]] set_property IOSTANDARD LVCM0S33 [get_ports a[3]] set_property PACKAGE_PIN R17[get_ports b[0]] set_property IOSTANDARD LVCM0S33 [get_ports b[0]] set_property PACKAGE_PIN T18[get_ports b[1]] set_property IOSTANDARD LVCM0S33 [get_ports b[1]] set_property PACKAGE_PIN U18[get_ports b[2]] set_property IOSTANDARD LVCM0S33 [get_ports b[2]] set_property PACKAGE_PIN R13[get_ports b[3]] set_property IOSTANDARD LVCM0S33 [get_ports b[3]] set_property PACKAGE_PIN J17 [get_ports AN0] set_property IOSTANDARD LVCM0S33 [get_ports AN0] set_property PACKAGE_PIN T8 [get_ports add_sous] set_property IOSTANDARD LVCM0S33 [get_ports T8] ```

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