Open terminal in work folder
Create new library with desired name, under technology file click "Attach to a existing technology library".
Select "gpdk180" under the technology library to attach.
Create new cellview from the File section (top left of window).
Give name to cellview and wait a few seconds to get a grid workarea. We Integrate all instances here.
To add an instance, click I. Browse for libraries and select gpdk_180. From component select NMOS and select. Hover over the black grid area to drop the selected item.
Select library as analogLib and cell vdc, to get dc_voltage source. Create two dc sources for the component. Go to instance and add ground, mentioned as GND (from the same library analogLib).
To connect different components of the circuit, use narrow wire (right beside the add instance icon in the taskbar)
Give value to both voltage sources, by editing values from the property editor. Simply left click on the component to open its property editor. After giving suitable values, click on the "check and save" icon once.
To go setup => Model libraries
Go to comp => / => TOOLS => PDK => gpdk180 v3.3 => models => spectre => gpdk.scs
This should put address of gpdk.scs into the Model Library Setup page. Under the "Section", choose "NN" from the dropdown. Click on Ok, to save NN. NN stands for Normal Normal.
Tasks
In the simulation window (ADE) choose AC DC trans.
Sweep variable : component parameter
Select voltage source at drain side, and choose voltage.
Change start, stop values.
Outputs => To be plotted => Select on schematic
Click on node to get current values, clicking on wires will give voltage values.
This should update the ADE L panel, under outputs window NMO/D will be added. D stands for Drain.
Click on play button (green) on the right hand side. This will open up a Visualization window with a graph of I (in milli amperes) vs V (in Voltage).
Click on voltage source, click on dc voltage.
Outputs => To be plotted => Select on design => Select node of gate.
For multiple sweeps at once.
Go to tools => Parametertic Analysis
Click on left hand side, add variable, dropdown, select V_gs. Define uppper and lower limit "from" and "to", Step Mode : "Auto", Total Steps : 5
I_d vs V_d multiple V_g
I_d vs V_d
I_d vs V_g multiple V_d
I_d vs V_g
Circuit Schematic
"gpdk" , "ADE L" full form
ADE : Analog Design Environment
gpdk : Generic Process Design Kit
Similar to NMOS
Maintain record of previous lab-sessions (Objective, schematic, output, graph, calculation)
Resistor : 1 kilo ohm
Pulse width : 2s
Why symbols
To make construction of complex circuits easier
Create pins (second from right in the top right corner)
V_dd V_ss and A are input pins
Y is an output pin
Check n save
Create => cellview => from cellview
Give top, bottom, left, right pins. Assign where each pin would be.
To use this as a black-box, create new cellview and import this using 'I'.
Run transient analysis, DC analysis.
Plot input and output, check where do the two graphs cross each other.
The crossing point should have voltage nearly equal to half of the input voltage
Inverter
Inverter_dc
Inverter_dc_with_input
Inverter_dc_with_multiple_input
Extra Lab on Tuesday (12th September)
Commands to open cadence
source_cshrs_new_12
virtuoso &
A window opens, click on new => cellview
To create NAND gate, use two pmos and to nmos, from the gpdk180_new library.
Circuit diagram is as follows :
NOTE : pMOS should be on top, nMOS should be on bottom.
Give inputs A, B such that all combinations of a two-bit system are available as inputs
As in, these combinations should exist [ (0,0), (0,1), (1,0), (1,1) ]
Create a symbol for the circuit, with A and B as left pins,V_dd as the top pin, GND as the bottom pin and C as the right pin (for output)
Close this window, from the CLI click on new_cellview and import the symbol created (from the roll_number wala folder).
Connect the pins with appropriate instances,
Period should be double that of width.
For voltage supply, choose a V_dc
Launch ADEL, import model libraries, choose NN. Select "tran" analysis
Submit hard copy of file by 12midnight, 15th september
Half Adder circuit
Half Adder symbol
Half Adder Output
Full Adder circuit
Full Adder symbol
Full Adder Output