HackMD
Verilog Lab 1 29/09/23
Introduction
Vivado HLx
Fullform of verilog is Verify Logic
HDL : Hardware Description Language
Only for digital circuits
Cadence is used to analyze and make circuits.
Verilog is a Programming language, to make a circuit accordingly.
Hardware Description Language
12 Experiments, scheduled in the next 2months.
Program Structure
- Gate Level Modelling
- simplest form
- Data Flow Modelling
- higher abstraction , assignment statements are used
- Behavioural Modelling
- highest level of abstraction, just truth table has to be provided
- always statement is used
We'll be working on Data Flow Modelling
A word file has to be prepped for each lab, showcasing the results of each lab. The wordfile should contain RTL (Resistor Transistor Logic).
Open home screen of Vivado, under the Quick Start box, click on Create Project.
Extension of extension file : .v file
Select Project Type as RTL Project
Select board, as the circuit has to be contructed on a board
Artix-7 AC701 Evaluation Platform
While defining the project, also add module name
The program manager page opens, open the file (visible under sources tab)
Run simulation => run behavioural simulation
RTL Analysis => To visualize what combination of gates we have built
To do
The wordfile should have the following :
- RTL Logic (schematic)
- Verilog code
The following gates have to be constructed :
- AND
- OR
- NOT
Instead of using Force Constant (under RTL Analysis), we can also make use of textbench to test if our given program is correct.
Use TestBench
Verilog Lab 2 06/10/23
Data Types
reg Data Type
Used to store data, values are retained until update
Vectors : Represent multi-bit buses
Memory : Used to model memories like ROM, RAM
Arrays : Collection of same types of variabes and accessed using the same name plus one or more indices
Parameters : constant values to be used in the program
Operators
Arithmetic
Logical ( negation, and, or )
Relational
Equality
Bitwise
Shift
Concatenation
Replication
Conditional
Viva Voice Questions on Operators
Difference between | and ||
Difference between >> and >>>
ans : >> preserved the sign bit triple >>> does not
Conditional
Symbol " ?: "
Internal Variable Monitoring System Tasks
We only use, only when required
$strobe
Displays simulation data at the end of current simulation time
$monitor
Each time a variable or expression changes values, the entire argument is displayed at the end of time step
$stop
Suspends the simulation and puts simulator in inactive mode
$finish
Makes the simulator exit and pass the control to the OS
Types of Assignments :
-
Continuous
Assign value when right hand side value changes
Implicit assignment
Independent of order
Executes in parallel and continues -
Procedural
Value placed on variable remains unchanges, unless a new procedural assignment updates the variable with a different value.
Multiple procedural blocks in a module can execute concurrently
Two types of procedural assignment :
a. Initial : Execution starts at zero, executes only once
b. Always : Repeats continuosly
Delays
- Regular Delay
- Intra assignment Delay
Block statements
- Begin-end : sequential execution
Type of assignments :
- Blocking : executed in order they are coded
- Non blocking : executed in parallel
Levels of Abstraction :
- Behavioural : Design of algorithm
- Dataflow : Design of equation
- Gate Level : Interconnection with Logic Gates
- Switch Level : Make use of transistors
To Do
Implement Half Adder and Full Adder using Verilog
Sum = A_bar.B + A.B_bar
Carry = A.B
4bit adder
4bit subtractor
Verilog Lab 3 13/10/23
Multiplexer
Multi Input, One Output
Design a 4x1 multiplexer
Further design 1x4 demux (data distributor)
We have covered half adder and full adder in combinational circuits
Write testbench for all cases (have select-line as inputs)
Generate sum-output of the full adder using a 4x1multiplexer.
Number of input bit required for full adder : 3
First draw out the structure for full adder, to generate required output
4x1 multiplexer requires 4inputs, but we have only 3 => To solve this, we try to minimize circuit
For 4inputs, 2select lines are also considered as inputs. Consider one input as 0, to minimize the circuit
Difficult way to achieve the same
Vary select lines, and depending on which select line is enabled, put signals S0, S1, S2, S3
Demux truth table
| S0 | S1 | Data Output Selected |
|---|---|---|
| 0 | 0 | A |
| 0 | 1 | B |
| 1 | 0 | C |
| 1 | 1 | D |
To Do
Try the same to generate carry-output of full adder
Decoder circuit
4x1 Mux
8x1 Mux
Generate half-adder sum
Make parity generator using Mux
Generate full-adder sum
Verilog Lab 4 10/11/23
Topic : Finite State Machines (FSM)
Course to follow on NPTEL : Hardware Modelling Using Verilog
| Present State | Next State |
|---|---|
| 00 | 01 |
| 01 | 11 |
| 11 | 00 |
How to implement state machines using flip-flops ?
If we do not have next state, we have been provided a mathematical function for the same, through which we can infer next states, through a graphical depiction of the function.
Find the following from the flip-flop
DA, DB, Current State, Next State
To practice :
Construct a full adder using half adders.
Content from Slides
Combinational and sequential circuits
Combinational
Output only depends only on the applied input values and not on the past history.
Sequential
Output not only depends on input, but also on state. The internal state also change with time. The number of states is finite and hence a sequential circuit is also referred to as a Finite State Machine.
Most of the practical circutis are sequential in nature, as having infinite states required infinite number of flip-flops.
FSM can be represented either in the form of a state table or in the form of a state transition diagram.
Examples :
- A circuit to detect 3 or more 1's in a serial bit stream.
- The bits are applied serially in synchronism with a clock.
- The output will become 1 whenever it detect 3 or more conscedcutie 1's in the stream
Types of FSM
-
Mealy
Output depends on state + inputs -
Moore
Output only depends on state
Example 1
There are 3 lamps, Red Green and Yellow that should glow cyclically with a fixed time interval.
Some observations:
- The FSM will have 3 states, corresponding to the glowing state of the lamps.
- They input set is null, state transition will occur whenever clock signal comes.
- This is a Moore Machine, since the lamp that will glow only depedns on the state, not on the inputs (here null)
| Denotion | State | Color |
|---|---|---|
| 00 | S_0 | Red |
| 01 | S_1 | Green |
| 10 | S_2 | Yellow |
2 Bits are required to model this.
Comment on the solution
The synthesis tool will generate five flip flops - 2 for state and 3 for light.
The three output lines are also getting stored in flip-flops
- We have used non-blocking assignment triggered by clock edge.
But actually we do not need sepeare flip-flops for the outputs, as the outputs can be directly generated from the state.
Example 2
Design of a serial parity detector.
0 will indicate "even number of 1's seen so far
1 will indicate "odd number of 1's seen so far.
Also a Moore Machine
Example 3
Design of a sequence detector
A circuit accepts a serial bit stream "s" as input and prouces a serial bit stream "z" as output.
Whenever the bit pattern "0110" appears in the input stream, ut outputs z=1, at all other times z=0.
Overlapping occurrencess of the pattern are also detected
This is a Mealy Machine
To Do
Design a sequence detector for 01110
State diagram for the sequence detector :
| State | Received Bit | Remark |
|---|---|---|
| s0 | - | Starting s0 |
| s1 | 0 | 1bit received successfully |
| s2 | 1 | 2bits received successfully |
| s3 | 1 | 3bits received successfully |
| s4 | 1 | 4bits received successfully |
Lab Exam Next Thursday (16 Nov)
Viva Questions
- Draw the FSM diagram for sequence detector for 1100
- What are mealy and moore FSM ?
- Draw truth table for JK Flip Flop and compare with SR Flip Flop.
- Make a Full Adder using Mux
- Can a multiplexer be called a universal gate ? Can we model every other function using mux ?
Simulation Questions
One had to submit a doc containing RTL Logic, Code snapshots, testbench code and testbench output.
- Sequence Detector
- Using a 3x8 decoder generate difference and carry of a subtractor.
- Four bit comparator
