A/D Convertor

• ADC - 成大資工 wiki
• VREF+ / VREF-

e.g. VREF- = 0V, VREF+ = 10V
10 bit resolution -> range = [0, 1023]
0V -> 0
5V -> 511
10V -> 1023

A/D conversion clock

• $T_{AD}$ (A/D Conversion time per bit)
  • $T_{AD}$ 愈小愈好，但是要大於最小
    $T_{AD}$

假設今天的頻率 (

$F_{OSC}$) 是 2.86 MHz, 則周期 (

$T_{OSC}$)會是

$\frac{1}{2.86\times {10}^6}\approx 0.35\mu s$，為了滿足最低 A/D Clock period (

$0.7\mu s$), 我們要把 conversion clock (

$T_{AD}$) 設成兩倍的

$T_{OSC}$

Acquisition time

Left/Right justified

Source

ADC Module

Input

• AN0~AN12

Note: 使用 ADC 的同時若發現其他 PORT 的 input 值怪怪的也許是誤把那些 PORT 設成 analog input (參考 ADCON1)

ADRES

ADCON0

ADCON1

ADCON2

Workflow

1. Configure the A/D module:

• Configure analog pins, voltage reference and digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON2)
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0)

2. Configure A/D interrupt (if desired):

• Clear ADIF bit
• Set ADIE bit
• Set GIE bit

3. Wait the required acquisition time (if required).
4. Start conversion, set GO/DONE bit (ADCON0 register)

如果使用 CCP2 的 special event trigger 則不用手動設置 GO/DONE bit

5. Wait for A/D conversion to complete
   (Wait for the A/D interrupt)
6. Read A/D Result registers (ADRESH:ADRESL);
   clear bit, ADIF, if required.
7. For next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2 TAD is required before the next acquisition starts.

CCP2 Module

• CCP2M3:CCP2M0 -> 1011 (CCP2CON<3:0>)
• Timer1 or Timer3 counter

Variable resistor

左右一邊接 5V，一邊接地，中間接輸入