🥶計數器 (Counter)
- 計數器是一種基本的數位電路元件,用於計算事件的發生次數或維護一個數字狀態。計數器通常可以根據其設計分為不同類型,主要包括同步計數器、異步計數器、向上計數器、向下計數器、以及雙向計數器。以下是這些計數器的簡介:
- 計數器的基本概念
計數器的功能:計數器能夠計算時間、事件或脈衝的數量,並以數字形式表示這些數量。
脈衝觸發:計數器通常是由時鐘信號觸發的,每當時鐘信號有變化(如上升沿或下降沿)時,計數器就會根據其設計的方式增加或減少計數值。
🔴連波進位計數器(Ripple_Carry_Counter)
- 架構:
連波進位計數器由D型觸發器和一個反向器組成T型正反器再由,串聯T型正反器即可完成。
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- 計數器的運作邏輯相對而言我覺得算是困難的,因為涉及了振盪之類的性質,某種程度上也算是有時序的影響,但是多加深入應用自然會有豁然開朗的一天!
👾加法器(Adder)
- 種類:加法器可分為基本的半加器,全加器(Ripple Carry Adder, CRA)、前瞻進位加法器(Carry Look-Ahead Adder, CLA)、進位選擇加法器(Carry Select Adder, CSA)等。
實務考量:在更高效能的應用中,會使用更複雜的設計如「跳躍進位」(Skip Carry)或「並行進位」(Parallel Carry)來進一步提升效率。
🔵半加法器(Half Adder)
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依據半法器的真值表和邏輯特性我們可以寫出以上的verilog代碼。
🔵全加法器(Full Adder)
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🔴四位元連波進位加法器(4 bits Ripple Full Adder)

- 架構
由全加法器依序串聯而成,每一個全加器的進位都會成為下一個全加器的進位輸入之一,而同時每一個全加器都會輸入對應位元的A和B做輸入,並輸出對應位元的Sum。
實作上我們採用階層方的設計,運用上面的全加器電路設計,我們可以輕易的調用出我們需要的數量,但是要注意到每個輸入和輸出的對應關係是否正確。
😈前瞻進位加法器(Carry Look-Ahead Adder, CLA)
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理由為可以知道,之間可以用來代換全加器,而其中尤其關鍵,皆可由此推導,以下是推導:
👿十進位加法器(Decimal Adder)


- 由於該電路涉及多個元件,邏輯關係更為複雜,也更容易出錯,寫程式碼的時候絕對要非常注意和小心!
👻減法器(Subtractor)
- 減法器(Subtractor)是一種數位邏輯電路,用於在二進制系統中執行減法運算。它和加法器一樣,是構建計算機和數位電路的基本組件之一。減法器可以根據應用需求分為「半減法器(Half Subtractor)」和「全減法器(Full Subtractor)」。
🔵半減法器(Half Subtractor)
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實作上是採用類似半加器的邏輯,唯一的差異就是借位時候輸入BA而不是A。
🔴全減法器(Half Subtractor)
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實作上是採用類似全加器的邏輯,但是為了因應borr的邏輯電路,做了比較多的wire去處理,也因此更容易出錯,需要特別留意!
😈連波借位全減法器(Ripple Borrow Full Subtractor)

實作上是採用類似連波全加器的邏輯,需要同時參照連波進位加法器和全減器
😼加減法器 (Adder-Subtractor)
-
加減法器(Adder-Subtractor)是一種可以同時執行加法與減法運算的數位電路。在電子工程和數位電路中,加減法器是一個非常重要的元件,常用於計算器、處理器中的算術邏輯單元(ALU),以及各種嵌入式系統中。其運作主要基於全加法器(Full Adder)電路,並利補碼(Two's Complement)來實現減法。

-
架構:
就是主要運用全加法器搭配二的補數的運算概念,因為A-B等同於A+B(B做二的補數)得到的數值,最後,就如同連波進位器我們也需要一個輸出來表達整體最終的進位到下一個運算中,我們可以藉由Cin和Cout的邏輯電路來判斷,當Cin為1時候代表兩數是在做減法,反之同理,但是最後就會注意到計算出來經常會有一個溢位的錯誤需要修正,關於這點我們採用xor(Cout,Cin)即可處理。
-
加減法器主要模組
- 參考波形圖:

🎃乘法器 (Multiplier)
- 在數位邏輯中,乘法器的目的是計算兩個數的乘積。對於二進制數,乘法的過程類似於十進制的乘法,透過逐位相乘和進位的方式來計算結果。即圖1
🔴二進位乘法器
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乘法器相對而言其實不是非常複雜,但是一旦位數更多了如何處理將會是一個值得留意的挑戰!
👹多工器 (Multiplexer, MUX)

-
多工器(Multiplexer,簡稱 MUX)和解多工器(Demultiplexer,簡稱 DEMUX)是數位電路中兩種重要的組件。它們在功能上是相對的,主要差異如下:
-
多工器 (MUX)
功能:多工器是一個選擇器,它根據控制信號選擇一個輸入信號並將其轉換為單個輸出。換句話說,MUX 會將多個輸入信號合併成一個輸出信號。
輸入與輸出:有多個數據輸入(如 2n2n 個)和一個輸出。控制信號的數量 nn 用於選擇哪一個輸入被傳遞到輸出。
示例:一個 2-to-1 多工器有兩個輸入、一個輸出和一個控制信號。根據控制信號的值,選擇其中一個輸入作為輸出。
-
解多工器 (DEMUX)
功能:解多工器的功能正好與多工器相反。它接收單個輸入信號並根據控制信號將其轉發到多個輸出中。也就是說,DEMUX 可以將一個數據信號分配到多個輸出。
輸入與輸出:有一個數據輸入和多個數據輸出(如 2n2n 個)。控制信號的數量 nn 用於選擇將數據輸出到哪一個具體的輸出端。
示例:一個 1-to-2 解多工器有一個輸入、兩個輸出和一個控制信號。根據控制信號的值,將輸入信號轉發到其中一個輸出。
-
總結
多工器 是用來選擇輸入信號並將其轉化為單一輸出;而 解多工器 則是用來將單一輸入信號分配到多個輸出。
在實際應用中,多工器通常用於數據路由,而解多工器則用於數據分發。
2 to 1 多工器

4-to-1 多工器

1-to-4 解多工器

- 輸入訊號I依據選擇線的開關被控制導入到特定的輸出口。
👽解碼器 (Decoder)
- 解碼器(Decoder) 是一種數位邏輯電路,它將二進制數字(通常是n位元)轉換為唯一的輸出信號,通常在一組2^n個輸出中只會有一個輸出為高電平(1),其餘則為低電平(0)。解碼器廣泛應用於計算機系統、存儲器解碼、數據選擇等領域。
🔵二對四解碼器(Decoder2_to_4)


module Decoder3_to_8(
input A, B, C, E,
output [7:0] D
);
wire BA, BB, BC, BE;
not (BA, A),
(BB, B),
(BC, C),
(BE, E);
nand (D[0], BA, BB, BC, BE),
(D[1], BA, BB, C, BE),
(D[2], BA, B, BC, BE),
(D[3], BA, B, C, BE),
(D[4], A, BB, BC, BE),
(D[5], A, BB, C, BE),
(D[6], A, B, BC, BE),
(D[7], A, B, C, BE);
endmodule
在概念和功能上解碼器很好理解,就是按照自己的需求可以藉由AND閘去設計類似開關的設計,輸入的邏輯會對應到特定的開關,關鍵在於如何在未來靈活應用到設計中。
編碼器 (Encoder)
🤙比較器(Comparator)
- 種類:比較器、幅度比較器(Magnitude Comparator)etc.
- 比較器(Comparator)是一種用於比較兩個數位信號的電路。它可以確定兩個輸入值之間的大小關係,並根據結果輸出相應的信號。比較器通常用於數據處理、數字控制系統和其他需要進行數據比較的應用。
🔵比較器(Comparator)

🔴大小比較器(Magnitude Comparator)

module Comparator4_to_4(
input [3:0]A, B,
output ALB, AGB, AEB
);
wire [3:0] FA, FB, FX;
wire [6:0] AND;
Comparator C3(A[3], B[3], FA[3], FB[3], FX[3]),
C2(A[2], B[2], FA[2], FB[2], FX[2]),
C1(A[1], B[1], FA[1], FB[1], FX[1]),
C0(A[0], B[0], FA[0], FB[0], FX[0]);
and (AND[6], FX[3], FA[2]),
(AND[5], FX[3], FB[2]),
(AND[4], FX[3], FX[2], FA[1]),
(AND[3], FX[3], FX[2], FB[1]),
(AND[2], FX[3], FX[2], FX[1], FA[0]),
(AND[1], FX[3], FX[2], FX[1], FB[0]),
( AEB, FX[3], FX[2], FX[1], FX[0]);
or (ALB, FA[3], AND[6], AND[4], AND[2]),
(AGB, FB[3], AND[5], AND[3], AND[1]);
endmodule
Sequential Logic Circuit(序向電路)

- 直到輸入信號切換狀態之前,都可以無限期的維持當前狀態,各種閂鎖與正反器的主要差異在於,輸入數以及這些輸入影響其狀態的方式,而閂鎖屬最基本的元件。

正反器(Flip-Flop)

- 藉由查看並比較激勵表與布林函數,我們可以系統化的設計序向電路(Sequential Logic Circuit)。
D型正反器

- 依據其設計指引,應該至少包含reset、CLK、EN(致能)和基本輸出入,其中需要留意的是當致能的時候,該元件才應該作用,否則應該保存當前狀態。除非此時啟動重置。

- Code

T型正反器

T型正反器的特點是,當T輸入為1的時候會將當前狀態反轉,當輸入為0的時候則保存當前狀態。


JK正反器
- JK正反器的狀態變化比較難用一句話描述,但是以下的特性表參閱可以確實幫助分析。



狀態表實作練習

在採用D型正反器的情況下使用卡諾圖化簡:

同步計數電路
module Show_Sync(
input CLK,
input CLRn,
output [6:0] Seg
);
wire CLKn;
wire [3:0] Q;
wire [6:0] Seg_tmp;
assign Seg=Seg_tmp;
Devide50M Div50 (CLK, CLRn, CLKn);
Sync02457 Syncnt(CLKn, CLRn, Q);
Seg7 seg (Q, Seg_tmp);
endmodule
module Devide50M(
input CLK,
input CLRn,
output CLKn
);
reg [25:0] Count;
reg CLKn_tmp;
assign CLKn = CLKn_tmp;
always@(posedge CLK or negedge CLRn)
begin
if(!CLRn)
begin
Count<=0;
CLKn_tmp<=0;
end
else if(Count==24999999)
begin
Count<=0;
CLKn_tmp<=~CLKn_tmp;
end
else
Count<=Count+1;
end
endmodule
module sync4(
input CLK,
input CLRn,
output [3:0] D
);
wire JK1;
wire JK2;
wire JK3;
wire [3:0] Dbar;
assign JK1=Dbar[1]&Dbar[2]&Dbar[3];
assign JK2=D[0]|D[2];
assign JK3=D[1]&D[2];
JK_flipflop
JKA(CLK, CLRn, JK1, D[3], D[0], Dbar[0]),
JKB(CLK, CLRn, JK2, 1'b1, D[1], Dbar[1]),
JKC(CLK, CLRn,D[1], D[1], D[2], Dbar[2]),
JKD(CLK, CLRn, JK3, 1'b1, D[3], Dbar[3]);
endmodule
module jk_ff(
input CLK,
input CLRn,
input J,
input K,
output reg Q,
output Qbar
);
assign Qbar=~Q;
always@(negedge CLK or negedge CLRn)
begin
if(!CLRn)
Q<=0;
else
case({J,K})
2'b00:Q<=Q;
2'b01:Q<=0;
2'b10:Q<=1;
2'b11:Q<=~Q;
endcase
end
endmodule
module Seg7(
input [3:0] Signal,
output reg [6:0] Seg
);
always@(*)begin
case(Signal)
4'h0 :Seg=7'b1000000;
4'h1 :Seg=7'b1111001;
4'h2 :Seg=7'b0100100;
4'h3 :Seg=7'b0110000;
4'h4 :Seg=7'b0011001;
4'h5 :Seg=7'b0010010;
4'h6 :Seg=7'b0000010;
4'h7 :Seg=7'b1111000;
4'h8 :Seg=7'b0000000;
4'h9 :Seg=7'b0010000;
4'hA:Seg=7'b0100000;
4'hB:Seg=7'b0000011;
4'hC:Seg=7'b1000110;
4'hD:Seg=7'b0100001;
4'hE:Seg=7'b0000110;
4'hF:Seg=7'b0001110;
endcase
end
endmodule



非同步清除3位元同步上數計數器

- 使用D型正反器實現,正反器功能包含清除功能,輸入由真值表化簡得出。
- 以下提供具體程式模組和測試模組:
FINITE STATE MACHINES(FSM)
- 有限狀態機描述的是一個電路其狀態可以依據暫存器的數量來展現。接續這個概念,通常有兩個類型 Moore Machines 和 Mealy Machines 其差異可以先觀察下圖。

- 前者輸出的信號只受到電路的當前狀態影響,但是後者輸出信號卻同時受到輸入信號和當前狀態影響。
FSM DESIGN EXAMPLE
- 課本有舉例一個範例來實現 FSM 的設計流程,讓我們開始來看看吧。
Football players are hustling between theathletic fields and the dining hall on Bravado Boulevard. They are tossingthe ball back and forth and aren’t looking where they are going either.Several serious injuries have already occurred at the intersection of these two roads, and the Dean of Students asks BenBitdiddle to install a trafficlight before there are fatalities.
暫存器(Register)
- 暫存器(Register)是數位電路中的一種基本元件,用來儲存二進位資料。它由一組觸發器(通常是D型觸發器)構成,能在時鐘信號的控制下儲存數據。暫存器常見於處理器、記憶體單元以及數位控制系統中。

32位元暫存器設計

- 功能說明:
由四個8位元暫存器 A, B, C, D組成,並且附帶一個暫存器V、以及選擇線,依據選擇線V會讀取A, B, C, D的資料,實現基礎的資料轉移。
module register #(parameter WIDTH=32, RLo=8)(
input CLK,
input CLRn,
input CE,
input [WIDTH-1:0] D,
input [NUM_SLsg-1:0] SLsg,
output [RLo-1:0] V,
output [RLo-1:0] Vbar,
output [WIDTH-1:0] Q,
output [WIDTH-1:0] Qbar
);
localparam NUM_SLsg=WIDTH/RLo;
wire [RLo-1:0] QA;
wire [RLo-1:0] QB;
wire [RLo-1:0] QC;
wire [RLo-1:0] QD;
wire [RLo-1:0]BQA;
wire [RLo-1:0]BQB;
wire [RLo-1:0]BQC;
wire [RLo-1:0]BQD;
assign Q={QD, QC, QB, QA};
assign Qbar={BQD, BQC, BQB, BQA};
register8 #(RLo)
regA (CLK, CLRn, CE, D[7:0], QA, BQA),
regB (CLK, CLRn, CE, D[15:8], QB, BQB),
regC (CLK, CLRn, CE, D[23:16], QC, BQC),
regD (CLK, CLRn, CE, D[31:24], QD, BQD);
register8_V #(WIDTH, RLo, NUM_SLsg)
regV (QA, QB, QC, QD, SLsg, V, Vbar);
endmodule
module Slect_Segment #(parameter RLo, NUM_SLsg)(
input [RLo-1:0] QA,
input [RLo-1:0] QB,
input [RLo-1:0] QC,
input [RLo-1:0] QD,
input [NUM_SLsg-1:0] SLsg,
output reg [RLo-1:0] TemV
);
always@(SLsg)
case(SLsg)
2'b00:TemV<=QA;
2'b01:TemV<=QB;
2'b10:TemV<=QC;
2'b11:TemV<=QD;
default: TemV = {RLo{1'b0}};
endcase
endmodule
module register8 #(parameter WIDTH)(
input CLK,
input CLRn,
input CE,
input [WIDTH-1:0] D,
output reg [WIDTH-1:0] Q,
output [WIDTH-1:0] Qbar
);
inverter #(WIDTH) invQ(Q, Qbar);
always @(posedge CLK or negedge CLRn) begin
if (!CLRn)
Q <= {WIDTH{1'b0}};
else if (CE)
Q <= D;
end
endmodule
module register8_V #(parameter WIDTH, RLo, NUM_SLsg)(
input [RLo-1:0] QA,
input [RLo-1:0] QB,
input [RLo-1:0] QC,
input [RLo-1:0] QD,
input [NUM_SLsg-1:0] SLsg,
output [WIDTH-1:0] Q,
output [WIDTH-1:0] Qbar
);
inverter #(WIDTH) invQ(Q, Qbar);
Slect_Segment #(RLo, NUM_SLsg)
S1 (QA, QB, QC, QD, SLsg, Q);
endmodule
module inverter #(parameter WIDTH)(
input [WIDTH-1:0] Qin,
output [WIDTH-1:0] Qout
);
assign Qout = ~Qin;
endmodule
8位元微處理機基本架構設計
- 支援四個功能 ADD, SUB, OR, AND,只有一個累加器(acc)和程式計數器(pc)。只使用一個CLK週期。
處理機結構
- Control Unit, CU, 採用簡化的FSM來達成硬體控制的功能。
- Arithmetic Logic Unit, ALU, 專注於ADD, SUB, OR, AND等運算功能的實現即可。
- Memory 採用唯讀記憶體存放指令。
- Registers 實現ACC, PC, IR 等功能為目標。