# MOVE SYSML Model Notes
## General
- Add pkg for Ground Segment (STR+Behavior) and move GS+Ops there :heavy_check_mark:

## Feedback MOVE-III IBD Overview
### General
- Flow Items w/o name
- One BlackBoxView & one WhiteBoxView Diagram

### ADCS
- i2c and spi are data lines -> check if adcs is connected with i2c and spi or only can → only can
- imu -> check if imu is soldered on the adcs board → it is
- unlinked ports: vbat in -> no vbat in right now

### COM
- missing power → vbat is power
- gnd ports → ask com

### STR
- is a separation of the power flow necessary for such a basic design?

### CDH
- unlinked ports: vabt in → no vbat in
- define missing connections → which connections
- gns modulke included? → no maybe the L4

## MOVE-III Discussion w/ Designer
### ADCS
- ADCS Board Standard Connector + Subsystem Connector why? → look up in PDR/ask EPS (Is every SSb placed with all the unneccessary data and power ports?) - in the model SSB is 150% board, investigate if everything unecessary can be deleted, Switched Mode Power Supply SMPS part of ADCS?
- VBAT for RW maybe - implemented
- Backplane - ADCS CAN
- Power Sensor Magnetroquer and RW for sure, other PowerSensors not necessary as these parts don't draw that much power - EPS Design Descision
- ADCS Board Power deleted and in adcs subsystem - nope to much work/to big diagram
- BDot Daemon delete (ADCS Daemon controlls everything)
- Add daemon for every sensor and hardware
- Geomagnetic Field Flow

### DEDRA
- bdd Breakdown structure
- idea feed is on the ssb, directly on the backplane
- feeac 1 pcb per sensor
- feeahv rather close to the sensor most probabaly in total 1 pcs

- bdd parts
- sensor box: 180v instead of 100v
- check hardware components package structure
- adc: position tbd, currently on feed, in the future potentually on feeac
- feed: ic=ion channel, gc =grid channel, nc = neutral channel, ec=electron channel → parts are not existing anymore, oszilator(not that important) and non volitaile flash memory is missing
- fpga ports: in+out data 3 adcs quad spi, 3.3V, in+out: data & adress to SRAM, GND
- feeahv: hv generation 5V instead of 3.3v; power converter located on every feeac (3x), produces out of 3,3V → 15V

- ibd dedra current
- feeahv pcb in dedra current diagram
- feed data: ic und ex amped siganl feeac instead of feed
- feeac data correct, adc missing
- SE Feedback
- FEEAC PCB bdd necessary? Is the high granity of the displayed parts necessary? Especially when it comes to ibds and Flows
- What is this DEDRA FEE PCB Stack for? Which PCB is placed on the SSB?
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### COM

- Structure
- Murgas one block + Power Sensor Murgas Module +
- 3.3V
- RS485 (basically UART but tranceiver chip necessary)
- RF Signal Antenna
- Right now Murgas is on extra Dulta board, on final not (special connector)
- RS485 Transceiver (UART, General I/O Port(transformed Signal))
- Ibd current: connect to connector with 3.3V

- Delete: DCDC Step down converter, RF Frontend, RF Transceiver, Power Sensor for RF Front, Power Sensor RF Trans, Temp Sensor, Power Sensor for Temp Sensor
- Flows
- Com Board only with 3.3V connected to the Backplane

### CDH
- Structure
- power sensors optional
- rtc battery
-
- Flows
- fram+mram add in power idb (3v3)
- gnss module power 3v3
- can in + out to backplane
- mram spi bidirectional
- rtc bidirectional 3,3 v flow to battery
- improvements: more detailed data lines for telemetry

### EPS

- structure
- bcr board: no digital anlog converter + no microcontroller; simplify diagrams
- no switch between bat board und backplane
- backplane: model as it is categorized in altium
- Model SSB

uvp manuel getriggert (reset pin)

pdr source for upgrades
(battery board und uvp nicht)

- SSB
- Is there a power out at the MCU?
- Check Ibd ADCS Board Power Overview
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