BMS circuit design
===
## Introduction
This project is for the Formula student competition. I designed this battery management system(BMS) to manage a 12V battery pack on a electrical race car and handle battery overcharge or overdischarge behaviours, which extend battery life and prevent explosion of batteries.

## CAD and Circuit
### ++3D model++
### ++Schematic++

### ++Layout++
 

## Chip
###
Datasheet: [S8209A_AN](https://www.ablic.com/en/doc/datasheet/battery_protection/S8209A_E.pdf)
Product name: S-8209ABB-T8T1U
### Spec
Overcharge voltage(Detection)(V~CU~): 4.35V
Overcharge voltage(Release)(V~CL~): 4.35V

Cell balance voltage(Detection)(V~BU~): 4.2V
Cell balance voltage(Release)(V~BL~): 4.2V

OverDischarge voltage(Detection)(V~DL~): 2.5V
OverDischarge voltage(Release)(V~DU~): 2.7V

---
## Operation and Schematic Explaination
This circuit is designed to deal with battery ++overcharge++ and ++overdischarge++. It will be explained by a practical example.

The symbol used below can be found [here](#Symbol)

### ==Normal status==
`CO`、`BO`、`CB` of three IC are all low impedance.
### ==Overcharge==
If voltage of BAT_3 reached V~BU~.
* *Step 1*
`CB` of `IC3` will be pulled up to VDD3 and turn `Q6` on.
Charge current is bypassed since `Q6` is on.

:::warning
:bulb:Bypassing the current doesn't mean BAT_3 is no longer charged. The charge rate is only slower than BAT_1, BAT_2.
:bulb: This mechanism means any V~DS~ >= V~BU~ will trigger `CB` and turn MOS on.
:::
* *Step 2*
For BAT_3, V~DS~ >= V~CU~, a series of actions will conduct.
If V~DS~ >= V~CU~:
→ `CO` = VSS3 (Set to high impedance)
→ `CTLC` of `IC2` = VSS3
→ `CO` of `IC2` = VSS2
→ `CTLC` of `IC1` = VSS2
→ `CO` of `IC1` = VSS1
→ Turn off `Q2` then turn off `Q8`
→ Charging loop is cut.
* *Step 3*
It is in normal status again if all BAT's V~DS~ <= V~BL~
### ==OverDischarge==
If BAT_1, BAT_3 are in normal status and BAT_2 is overdischarged.

* *Step 1*
V~DS~ of `Q5` is below 2.5V

* *Step 2*

`DO` of `IC2` is set to high impedance, indicate `IC1` by `CTLD`.

* *Step 3*

The voltage of `IC1`'s `CTLD` drop will cause `DO` in High-Z and `CB` is on high-voltage:
`CB` on → opens `Q3` and BAT_1 is short circuit
`DO` high → turns off `Q1`

:::warning
:fire:Heat Problem
When BAT_1 is short circuit, heat is generated.

On the PCB layout, it can be found that the pads of `R6` `R11` `R18` are larger than normal ones. This is for heat dissipation and high walts resistors are selected to withstand the temperture rise.
:::
* *Step 4*
Since `Q1` is turned off, `Q9` will be turned off. The loop is cut.

## Symbol
Overcharge voltage(Detection): V~CU~
Overcharge voltage(Release): V~CL~

Cell balance voltage(Detection: V~BU~
Cell balance voltage(Release): V~BL~

OverDischarge voltage(Detection): V~DL~
OverDischarge voltage(Release): V~DU~

Mosfet Drain to Source voltage: V~DS~

VSS1: VSS of IC1
VSS2: VSS of IC2
VSS3: VSS of IC3