---
breaks: false
---
# OpenVAF, OSDI and VerilogAE


Verilog-A is the industry-standard language for implementing compact models.
Existing solutions have many shortcomings and even struggle to compile the Silicon Integration Initiative [Compact Model Coalition](https://si2.org/cmc/) standard models.
While CMC models are always implemented in Verilog-A, most users do not actually use that Verilog-A code.
Instead, circuit simulators manually implement each model in a labor-intensive and error-prone process.
Furthermore, more advanced tooling that is useful for parameter extraction or research is also unavailable.

SemiMod is developing a state-of-the-art compiler to provide the next generation of Verilog-A tooling.
Our aim is to bring the advancements made in compiler-construction for other languages to Verilog-A.
Our solution consists of 3 components:

* OpenVAF: Flexible general purpose Verilog-A compiler
* OSDI: Simulator-independent model interface
* VerilogAE: Python library for Parameter Extraction and Reseach applications

If your circuit simulation environment needs a state-of-the-art Verilog-A compiler, contact us and we will help to integrate OpenVAF into your simulation workflow.

## OpenVAF

OpenVAF forms the core of our technology stack. It is a general purpose Verilog-A compiler with a flexible architecture. This allows OpenVAF to be used as a standalone executable to compile Verilog-A models for all circuit simulators using OSDI, a simulator specific interface or as part of VerilogAE. Compared to traditional compilers, OpenVAF provides a better user experience by offering:

* Helpful diagnostics
* more comprehensive standard compliance
* faster compilation and simulation

OpenVAF takes great care to implements high quality diagnostic messages that provide detailed information to users. Furthermore, OpenVAF is designed to be error resilient. This allows the compiler to detect all errors at once, instead of aborting after a single error, like other compilers do.

Another important component of the user-experience is documentation.
The documentation of Verilog-A already exists in the form of the language standard.
To ensure consistent behavior, OpenVAF aims to closely implement the language standard, where possible.
For example, OpenVAF is able to correctly compile **all CMC models without modification** and correctly handle **higher-order derivatives** to ensure `ddx` can be used everywhere.
However, due to limitations of the simulators, some features can not be supported properly. SemiMod is committed to ensuring that in these cases
helpful diagnostics are emitted by OpenVAF and to
[document](https://man.sr.ht/~dspom/openvaf_doc/language_support.md) these deviations.

Finally, the most impactful improvement offered by OpenVAF is the improvement in compilation and simulation speed.
OpenVAF internally functions more like a C-compiler than a traditional Verilog-A compiler.
As a result, it avoids lots of repeated effort and can compile (almost) all CMC models under 2 seconds.
This approach also allows more complex analysis algorithms which allow OpenVAF to generate much more efficient derivatives and as a result simulations are 30%-300% faster compared to traditional compilers.
This allows OpenVAF compiled models to **match the speed of handwritten models**.

## OSDI

OSDI is a simulator independent interface for device models. OpenVAF compiles Verilog-A files to shared libraries that conform to OSDI. The interface is designed to be very modular, so it can be used regardless of the details of the simulators. Compared to traditional compilers, different simulators won't have to reimplement large components of the compiler, instead they can just implement a compatibility layer between OSDI and the internal interface.

SemiMod can assist you as a partner during this process.

## VerilogAE

VerilogAE is a python library that makes individual model equations available in python.
Compared to a circuit simulator, there is no solver involved.
Instead, the user needs to provide all potential used for an equation.
The intended use-case is curve-fitting during parameter extraction or investigations of model internals.
DMT integrates VerilogAE directly to offer a comprehensive suite of tooling for device engineers.