Dear Tim,

thanks you for your reply.

The two Verilog-A models in the Skywater PDK can be compiled using our compiler, however
small changes according to [#10](https://github.com/google/skywater-pdk-libs-sky130_fd_pr_reram/issues/10) would
be needed.

> What type of funding are you looking for?

We are looking for funding for one position to continue working on implementing, debugging and extending the Verilog-A features of Ngspice and Xyce
using our compiler.

> From what I have seen so far, a lot of what analog designers say are essential have turned out to be optional or even totally unneeded.
The currently available open source tools (xschem, ngspice/xyce, others) seem capable of creating even high performance analog circuits.

The Skywater PDK uses SGP models for BJTs and a specific BSIM version for FETs which are hand-implemented into Ngspice, hence designers have no issues.
All circuit simulators implement only specific model versions as model implementation is a time- and knowledge-intensive task.
For example, the newest BSIM version is 4.8.2, ngspice implements up to 4.8.1 and Xyce implements only 4.6.1.

If one requires more up to date model versions, or more accurate models, Verilog-A support is mandatory.
For example, most proprietary PDKs would not run with Ngspice/Xyce as they use other models/model versions.
It is only a matter of time until the open-source designers run into this problem ([#8](https://github.com/google/skywater-pdk-libs-sky130_fd_pr_reram/issues/8)).
For a complete toolchain for designing analog circuits, a modern and supported Verilog-A compiler is not optional.

Presently, Xyce is using ADMS, which has not been maintained for a long time and has many technical shortcomings.
Both the Xyce and the NGSPICE developers are therefore [looking for alternatives](https://www.mos-ak.org/silicon_valley_2021/presentations/Verley_MOS-AK_SV_21.pdf).
They are engaged with us and looking to use our compiler as their primary Verilog-A solution. This will fill an important gap in the open-source tools.

In the future, Verilog-A will enable also other use-cases, i.e. to wrap a complete PDK in Verilog-A files and
thereby enable to use the same PDK in different simulators (addresses issues like [#186](https://github.com/google/skywater-pdk/issues/186)).
This would also help the OpenFASoC team, since then only one generator is needed for all simulators.

> Is there a story about how your work can improve digital performance by better characterisation of standard cells or similar?

As we are mainly involved in analog design, we do not know the process to charaterise the standard cells. But better modells allow better usage of transistors in general.
Additionally, if there are aims to use FinFET technologies, models like BSIM-CMG and BSIM-IMG are needed.
These are currently not supported by NGSPICE and Xyce only supports them by compiling the Verilog-A file with the abandoned ADMS compiler.

Verilog-A is a subset of [Verilog-AMS](https://www.accellera.org/images/downloads/standards/v-ams/VAMS-LRM-2-4.pdf). Verilog-AMS is intended to allow mixed
signal modelling in a single HDL. Currently the only simulator that acctually supports this is Cadence Spectre. Offering this mixed signal capability as an open-source
tool could be an interesting longterm goal for our compiler. However this would require a large time investment.

> You probably want to work on your publicity, as I have never seen anyone bring up this work on the SkyWater slack channel, despite there being a large number of analog designers on the channel.

Currently we have not published a prototype that is actually usable for normal simulations, hence this is expected. Our compiler is a fairly complex project (approach 100k LOC)
that has been in development for a while. We hope that once we publish a working prototype with Ngspice integration in the next month, we will recive more publicity.

We will follow your recommendation to mirror our repos on GitHub.

Best regards,

Markus