# TP 6
###### tags: `TPS`
gen_binaire.vhd
```c
library ieee;
use ieee.std_logic_1164.all;
entity gen_binaire is
port (
clock : in std_logic;
register_output : out std_logic
);
end;
architecture behave of gen_binaire is
signal register_state : std_logic_vector(1 to 10) := "0000000001";
begin
register_output <= register_state(10);
process(clock)
begin
if rising_edge(clock) then
register_state(2 to 10) <= register_state(1 to 9);
register_state(1) <= register_state(3) xor register_state(10);
end if;
end process;
end;
```
gen_binaire_tb.vhd
```c
library ieee;
use ieee.std_logic_1164.all;
entity gen_binaire_tb is
end;
architecture testbench of gen_binaire_tb is
signal clock : std_logic := '0';
signal register_output : std_logic;
constant BIT_CLOCK_PERIOD : time := 200 ns;
begin
dut : entity work.gen_binaire port map(clock => clock , register_output => register_output);
clock <= not(clock) after BIT_CLOCK_PERIOD /2;
end;
```
mapping.vhd
```c
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mapping is port (
clock : std_logic := '0' ;
bit_couple : in unsigned (1 downto 0);
I : out integer range -1 to 1
);
end;
architecture behave of mapping is
begin
with bit_couple select
I <=
-1 when "01",
-1 when "11",
1 when others;
end;
```
mapping_tb.vhd
```c
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mapping_tb is
end;
architecture testbench of mapping_tb is
constant DELTA_TIME : time := 20 ns;
signal bit_couple : unsigned(1 downto 0);
signal I : integer range -1 to 1;
begin
dut : entity work.mapping port map(bit_couple => bit_couple, I => I);
process
begin
wait for DELTA_TIME;
bit_couple <= "00";
wait for DELTA_TIME; bit_couple <= "01";
wait for DELTA_TIME; bit_couple <= "10";
wait for DELTA_TIME; bit_couple <= "11";
wait;
end process;
end;
```
```c
sum := 0;
for k in 0 to NUMBER_OF_COEFFS-1 loop
sum := sum + H(k) * x(NUMBER_OF_COEFFS-1-k);
end loop;
y <= sum;
```
```c
if falling_edge(clock) then
sum := 0;
for i in 0 to NUMBER_OF_COEFFS-1 loop
s(i) := x(i) * H(i);
sum := sum + s(i);
end loop;
y <= sum;
end if;
```
```c
module1 : entity gen_horloge is
generic(
FREQ : frequency_type := freq_10_MHz
);
port(
clock : instd_logic;
pulse : outstd_logic
);
end;
```
```c
module2 : entity div_freq_by_2 is
port(
clock :instd_logic;
clock_divided :outstd_logic
);
end;
module2 : entity work.div_freq_by_2 port map(clock => sample_clock, clock_divided => bit_clock);
```
– module 3 : gen_binaire.vhd
```c
entity gen_binaire is
port (
clock : in std_logic;
register_output : out std_logic
);
end;
```
```c
module4 : entity serial_2_parallel is
port (
serial_bit , clock : in std_logic ;
parallel_bit : out unsigned (1 downto 0)
);
end;
module4 : entity work.serial_2_parallel(bit_data => bit_couple, bit_clock)
```
```c
module5 : entity mapping is
port (
bit_couple : in unsigned (1 downto 0) ;
I : out integer range -1 to 1
);
end;
module5 : entity
```
```c
module6 : entity oversampling is
port (
clock_sample : in std_logic ;
symbol : in integer range -1 to 1;
symbol_oversampled : out integer range -1 to 1
);
end;
module6 : entity work.oversampling port map(clock_sample => sample_clock, symbol=>I, symbol_oversamppled=>I_oversampled);
```
module 7 : filtrage.vhd
```c
module7 : entity filtrage is
port(
clock : in std_logic;
x0 : in integer range -1 to 1;
y : out integer range -8192 to 8191 := 0
);
end;
module7 : entity work.filtrage port map(clock => sample_clock, x0=>I_oversampled, y=>I_filtered);
```
```c
module8 : entity scaling is port(
centered_y : in integer range -8192 to 8191 := 0;
positive_y : out integer range 0 to 163835
);
end;
module8 : entity work.scaling port map (centered_y =>I_filtered, positive_y=>dac_data);
```
liste des modules a mettre en chaine:
```c
module1 : entity work.gen_horloge port map(clock => clock_50_M, pulse => sample_clock);
module2 : entity work.div_freq_by_2 port map(clock => sample_clock, clock_divided => bit_clock);
module2bis : entity work.div_freq_by_2 port map(clock => bit_clock, clock_divided => symbol_clock);
module3 : entity work.gen_binaire port map(clock => bit_clock, register_output => bit_data);
module4 : entity work.serial_2_parallel port map(serial_bit => bit_data, clock => bit_clock, parallel_bit => bit_couple);
module5 : entity work.mapping port map(bit_couple => bit_couple, I => I);
module6 : entity work.oversampling port map(clock_sample => sample_clock, symbol=>I, symbol_oversampled=>I_oversampled);
module7 : entity work.filtrage port map(clock => sample_clock, x0 => I_oversampled, y => I_filtered);
module8 : entity work.scaling port map (centered_y => I_filtered, positive_y => dac_data);
```
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