# Lab2: RISC-V RV32I[MA] emulator with ELF support
###### tags: `Computer Architecture`
## Sum of First N Natural Numbers
### **Problem Discuss**
The Assemble code without compiler optimization
``` =
.file "test.c"
.option nopic
.text
.align 2
.globl main
.type main, @function
main:
addi sp,sp,-32
sw ra,28(sp)
sw s0,24(sp)
addi s0,sp,32
li a5,10
sw a5,-28(s0)
sw zero,-24(s0)
li a5,1
sw a5,-20(s0)
j .L2
.L3:
lw a4,-24(s0)
lw a5,-20(s0)
add a5,a4,a5
sw a5,-24(s0)
lw a5,-20(s0)
addi a5,a5,1
sw a5,-20(s0)
.L2:
lw a4,-20(s0)
lw a5,-28(s0)
ble a4,a5,.L3
lw a0,-24(s0)
call printInt
nop
lw ra,28(sp)
lw s0,24(sp)
addi sp,sp,32
jr ra
.size main, .-main
.section .rodata
.align 2
.LC0:
.word 1
.word 10
.word 100
.word 1000
.word 10000
.word 100000
.word 1000000
.word 10000000
.word 100000000
.text
.align 2
.globl printInt
.type printInt, @function
printInt:
addi sp,sp,-96
sw s0,92(sp)
addi s0,sp,96
sw a0,-84(s0)
li a5,1073750016
sw a5,-40(s0)
lui a5,%hi(.LC0)
lw t1,%lo(.LC0)(a5)
addi a4,a5,%lo(.LC0)
lw a7,4(a4)
addi a4,a5,%lo(.LC0)
lw a6,8(a4)
addi a4,a5,%lo(.LC0)
lw a0,12(a4)
addi a4,a5,%lo(.LC0)
lw a1,16(a4)
addi a4,a5,%lo(.LC0)
lw a2,20(a4)
addi a4,a5,%lo(.LC0)
lw a3,24(a4)
addi a4,a5,%lo(.LC0)
lw a4,28(a4)
addi a5,a5,%lo(.LC0)
lw a5,32(a5)
sw t1,-76(s0)
sw a7,-72(s0)
sw a6,-68(s0)
sw a0,-64(s0)
sw a1,-60(s0)
sw a2,-56(s0)
sw a3,-52(s0)
sw a4,-48(s0)
sw a5,-44(s0)
li a5,900001792
addi a5,a5,-1792
sw a5,-20(s0)
sw zero,-32(s0)
lw a5,-84(s0)
bgez a5,.L5
lw a5,-40(s0)
li a4,45
sb a4,0(a5)
lw a5,-84(s0)
neg a5,a5
sw a5,-84(s0)
.L5:
li a5,8
sw a5,-24(s0)
j .L6
.L14:
li a5,-1
sw a5,-36(s0)
li a5,9
sw a5,-28(s0)
j .L7
.L11:
lw a4,-84(s0)
lw a5,-20(s0)
blt a4,a5,.L8
li a5,1
sw a5,-32(s0)
lw a5,-28(s0)
sw a5,-36(s0)
lw a4,-84(s0)
lw a5,-20(s0)
sub a5,a4,a5
sw a5,-84(s0)
.L8:
lw a4,-28(s0)
li a5,1
beq a4,a5,.L9
lw a5,-24(s0)
slli a5,a5,2
addi a4,s0,-16
add a5,a4,a5
lw a5,-60(a5)
lw a4,-20(s0)
sub a5,a4,a5
j .L10
.L9:
lw a5,-24(s0)
addi a5,a5,-1
slli a5,a5,2
addi a4,s0,-16
add a5,a4,a5
lw a5,-60(a5)
lw a4,-20(s0)
sub a5,a4,a5
.L10:
sw a5,-20(s0)
lw a5,-28(s0)
addi a5,a5,-1
sw a5,-28(s0)
.L7:
lw a5,-28(s0)
bgtz a5,.L11
lw a4,-36(s0)
li a5,-1
beq a4,a5,.L12
lw a5,-36(s0)
andi a5,a5,0xff
addi a5,a5,48
andi a4,a5,0xff
lw a5,-40(s0)
sb a4,0(a5)
j .L13
.L12:
lw a5,-32(s0)
beqz a5,.L13
lw a5,-40(s0)
li a4,48
sb a4,0(a5)
.L13:
lw a5,-24(s0)
addi a5,a5,-1
sw a5,-24(s0)
.L6:
lw a5,-24(s0)
bgez a5,.L14
nop
lw s0,92(sp)
addi sp,sp,96
jr ra
.size printInt, .-printInt
.ident "GCC: (xPack GNU RISC-V Embedded GCC, 64-bit) 8.2.0"
```
Execute program
```
$ riscv-none-embed-gcc -march=rv32im -mabi=ilp32 -nostdlib -o test1 test1.c
$ ./emu-rv32i test1
>>> Execution time: 1778 ns
>>> Instruction count: 3 (IPS=1687289)
>>> Jumps: 0 (0.00%) - 0 forwards, 0 backwards
>>> Branching T=0 (-nan%) F=0 (-nan%)
```
I find the emulator only executes 3 instructions. It is abnormal. So I use GDB and define DEBUG_OUTPUT to debug.
I find the reason why emulator only executes 3 instruction is stack pointer. Because when test1 program is loaded into emulator,the stack pointer is zero. Observe assemble code in line 8 and 9.
``` =8
addi sp,sp,-32
sw ra,28(sp)
```
The sp will be -48, and store s0 to -48 address. It will result in exception.
### **Solution**
I write simple the setup code to initialize the register and section.
``` =
# Define constants
.section .text
.align 2
.globl _start
_start:
li x1, 0
li x2, 0
li x3, 0
li x4, 0
li x5, 0
li x6, 0
li x7, 0
li x8, 0
li x9, 0
li x10, 0
li x11, 0
li x12, 0
li x13, 0
li x14, 0
li x15, 0
li x16, 0
li x17, 0
li x18, 0
li x19, 0
li x20, 0
li x21, 0
li x22, 0
li x23, 0
li x24, 0
li x25, 0
li x26, 0
li x27, 0
li x28, 0
li x29, 0
li x30, 0
li x31, 0
init_stack:
/* set stack pointer */
la sp, _stack
SystemInit:
jal main
j SystemExit
SystemExit:
/* End simulation */
ecall
```
linker script tells the compiler how to arrange the section location in memory.
``` =
OUTPUT_ARCH( "riscv" )
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x1000;
/*****************************************************************************
* Define memory layout
****************************************************************************/
MEMORY {
mem : ORIGIN = 0x00000000, LENGTH = 0x00000100
imem : ORIGIN = 0x00000100, LENGTH = 0x00010000
}
/* Specify the default entry point to the program */
ENTRY(_start)
/*****************************************************************************
* Define the sections, and where they are mapped in memory
****************************************************************************/
SECTIONS {
.comment : {
*(.comment);
*(.comment.*);
} > mem
.text : {
setup.o(.text);
*(.text);
*(.text.*);
} > imem
.rodata : {
__rodata_start = .;
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
__rodata_end = .;
} > imem
.data : {
. = ALIGN(4);
__data_start = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
__data_end = .;
} > imem
.stack : {
. = ALIGN(4);
_stack_end = .;
. += _STACK_SIZE;
_stack = .;
__stack = _stack;
} > imem
}
```
Compile without compiler optimization and execute
```
$ riscv-none-embed-gcc -march=rv32i -mabi=ilp32 -O3 -nostdlib -c setup.s
$ riscv-none-embed-gcc -w test.c setup.o -march=rv32i -mabi=ilp32 -O3 -nostdlib -Tlinker.ld -o test
$ ./emu-rv32i test
55
>>> Execution time: 11947 ns
>>> Instruction count: 321 (IPS=26868669)
>>> Jumps: 101 (31.46%) - 73 forwards, 28 backwards
>>> Branching T=88 (82.24%) F=19 (17.76%)
```
Compile with compiler optimization and execute
```
$ riscv-none-embed-gcc -march=rv32i -mabi=ilp32 -nostdlib -c setup.s
$ riscv-none-embed-gcc -w test.c setup.o -march=rv32i -mabi=ilp32 -nostdlib -Tlinker.ld -o test
$ ./emu-rv32i test
55
>>> Execution time: 50557 ns
>>> Instruction count: 2003 (IPS=39618648)
>>> Jumps: 293 (14.63%) - 191 forwards, 102 backwards
>>> Branching T=203 (70.00%) F=87 (30.00%)
```
In this program, it spends a lot of instructions on print integer.
* **Memory Layout**
### GNU Toolchain
C code
``` =
void main(){
int N = 10,i,sum=0;
for(i=1;i<=N;i=i+1)
sum = sum +i;
printInt(sum) ;
}
void printInt(int result){
volatile char* tx = (volatile char*) 0x40002000;
int dict[9] ={1,10,100,1000,10000,100000,1000000,10000000,100000000};
int mx = 900000000,i,j,isprint=0;
if(result >> 31){
*tx = '-';
result = -result;
}
for(i=8;i>=0;i=i-1){
int print = -1;
for(j=9;j>=1;j--){
if ( result >= mx){
isprint =1;
print = j;
result = result - mx;
}
mx = (j!=1)? (mx - dict[i]):(mx-dict[i-1]);
}
if(print!=-1) *tx = (print+48);
else if (isprint) *tx = 48;
}
}
```
**objdump**
```
$riscv-none-embed-objdump -d test
```
output without compiler Optimization
```
test: file format elf32-littleriscv
Disassembly of section .text:
00000100 <_start>:
100: 00000093 li ra,0
104: 00000113 li sp,0
108: 00000193 li gp,0
10c: 00000213 li tp,0
110: 00000293 li t0,0
114: 00000313 li t1,0
118: 00000393 li t2,0
11c: 00000413 li s0,0
120: 00000493 li s1,0
124: 00000513 li a0,0
128: 00000593 li a1,0
12c: 00000613 li a2,0
130: 00000693 li a3,0
134: 00000713 li a4,0
138: 00000793 li a5,0
13c: 00000813 li a6,0
140: 00000893 li a7,0
144: 00000913 li s2,0
148: 00000993 li s3,0
14c: 00000a13 li s4,0
150: 00000a93 li s5,0
154: 00000b13 li s6,0
158: 00000b93 li s7,0
15c: 00000c13 li s8,0
160: 00000c93 li s9,0
164: 00000d13 li s10,0
168: 00000d93 li s11,0
16c: 00000e13 li t3,0
170: 00000e93 li t4,0
174: 00000f13 li t5,0
178: 00000f93 li t6,0
0000017c <init_stack>:
17c: 00001117 auipc sp,0x1
180: 26410113 addi sp,sp,612 # 13e0 <__stack>
00000184 <SystemInit>:
184: 00c000ef jal ra,190 <main>
188: 0040006f j 18c <SystemExit>
0000018c <SystemExit>:
18c: 00000073 ecall
00000190 <main>:
190: fe010113 addi sp,sp,-32
194: 00112e23 sw ra,28(sp)
198: 00812c23 sw s0,24(sp)
19c: 02010413 addi s0,sp,32
1a0: 00a00793 li a5,10
1a4: fef42223 sw a5,-28(s0)
1a8: fe042423 sw zero,-24(s0)
1ac: 00100793 li a5,1
1b0: fef42623 sw a5,-20(s0)
1b4: 0200006f j 1d4 <main+0x44>
1b8: fe842703 lw a4,-24(s0)
1bc: fec42783 lw a5,-20(s0)
1c0: 00f707b3 add a5,a4,a5
1c4: fef42423 sw a5,-24(s0)
1c8: fec42783 lw a5,-20(s0)
1cc: 00178793 addi a5,a5,1
1d0: fef42623 sw a5,-20(s0)
1d4: fec42703 lw a4,-20(s0)
1d8: fe442783 lw a5,-28(s0)
1dc: fce7dee3 bge a5,a4,1b8 <main+0x28>
1e0: fe842503 lw a0,-24(s0)
1e4: 018000ef jal ra,1fc <printInt>
1e8: 00000013 nop
1ec: 01c12083 lw ra,28(sp)
1f0: 01812403 lw s0,24(sp)
1f4: 02010113 addi sp,sp,32
1f8: 00008067 ret
000001fc <printInt>:
1fc: fa010113 addi sp,sp,-96
200: 04812e23 sw s0,92(sp)
204: 06010413 addi s0,sp,96
208: faa42623 sw a0,-84(s0)
20c: 400027b7 lui a5,0x40002
210: fcf42c23 sw a5,-40(s0)
214: 3bc02303 lw t1,956(zero) # 3bc <__rodata_start>
218: 3bc00713 li a4,956
21c: 00472883 lw a7,4(a4)
220: 3bc00713 li a4,956
224: 00872803 lw a6,8(a4)
228: 3bc00713 li a4,956
22c: 00c72503 lw a0,12(a4)
230: 3bc00713 li a4,956
234: 01072583 lw a1,16(a4)
238: 3bc00713 li a4,956
23c: 01472603 lw a2,20(a4)
240: 3bc00713 li a4,956
244: 01872683 lw a3,24(a4)
248: 3bc00713 li a4,956
24c: 01c72703 lw a4,28(a4)
250: 3bc00793 li a5,956
254: 0207a783 lw a5,32(a5) # 40002020 <__stack+0x40000c40>
258: fa642a23 sw t1,-76(s0)
25c: fb142c23 sw a7,-72(s0)
260: fb042e23 sw a6,-68(s0)
264: fca42023 sw a0,-64(s0)
268: fcb42223 sw a1,-60(s0)
26c: fcc42423 sw a2,-56(s0)
270: fcd42623 sw a3,-52(s0)
274: fce42823 sw a4,-48(s0)
278: fcf42a23 sw a5,-44(s0)
27c: 35a4f7b7 lui a5,0x35a4f
280: 90078793 addi a5,a5,-1792 # 35a4e900 <__stack+0x35a4d520>
284: fef42623 sw a5,-20(s0)
288: fe042023 sw zero,-32(s0)
28c: fac42783 lw a5,-84(s0)
290: 0007de63 bgez a5,2ac <printInt+0xb0>
294: fd842783 lw a5,-40(s0)
298: 02d00713 li a4,45
29c: 00e78023 sb a4,0(a5)
2a0: fac42783 lw a5,-84(s0)
2a4: 40f007b3 neg a5,a5
2a8: faf42623 sw a5,-84(s0)
2ac: 00800793 li a5,8
2b0: fef42423 sw a5,-24(s0)
2b4: 0f00006f j 3a4 <printInt+0x1a8>
2b8: fff00793 li a5,-1
2bc: fcf42e23 sw a5,-36(s0)
2c0: 00900793 li a5,9
2c4: fef42223 sw a5,-28(s0)
2c8: 08c0006f j 354 <printInt+0x158>
2cc: fac42703 lw a4,-84(s0)
2d0: fec42783 lw a5,-20(s0)
2d4: 02f74263 blt a4,a5,2f8 <printInt+0xfc>
2d8: 00100793 li a5,1
2dc: fef42023 sw a5,-32(s0)
2e0: fe442783 lw a5,-28(s0)
2e4: fcf42e23 sw a5,-36(s0)
2e8: fac42703 lw a4,-84(s0)
2ec: fec42783 lw a5,-20(s0)
2f0: 40f707b3 sub a5,a4,a5
2f4: faf42623 sw a5,-84(s0)
2f8: fe442703 lw a4,-28(s0)
2fc: 00100793 li a5,1
300: 02f70263 beq a4,a5,324 <printInt+0x128>
304: fe842783 lw a5,-24(s0)
308: 00279793 slli a5,a5,0x2
30c: ff040713 addi a4,s0,-16
310: 00f707b3 add a5,a4,a5
314: fc47a783 lw a5,-60(a5)
318: fec42703 lw a4,-20(s0)
31c: 40f707b3 sub a5,a4,a5
320: 0240006f j 344 <printInt+0x148>
324: fe842783 lw a5,-24(s0)
328: fff78793 addi a5,a5,-1
32c: 00279793 slli a5,a5,0x2
330: ff040713 addi a4,s0,-16
334: 00f707b3 add a5,a4,a5
338: fc47a783 lw a5,-60(a5)
33c: fec42703 lw a4,-20(s0)
340: 40f707b3 sub a5,a4,a5
344: fef42623 sw a5,-20(s0)
348: fe442783 lw a5,-28(s0)
34c: fff78793 addi a5,a5,-1
350: fef42223 sw a5,-28(s0)
354: fe442783 lw a5,-28(s0)
358: f6f04ae3 bgtz a5,2cc <printInt+0xd0>
35c: fdc42703 lw a4,-36(s0)
360: fff00793 li a5,-1
364: 02f70063 beq a4,a5,384 <printInt+0x188>
368: fdc42783 lw a5,-36(s0)
36c: 0ff7f793 andi a5,a5,255
370: 03078793 addi a5,a5,48
374: 0ff7f713 andi a4,a5,255
378: fd842783 lw a5,-40(s0)
37c: 00e78023 sb a4,0(a5)
380: 0180006f j 398 <printInt+0x19c>
384: fe042783 lw a5,-32(s0)
388: 00078863 beqz a5,398 <printInt+0x19c>
38c: fd842783 lw a5,-40(s0)
390: 03000713 li a4,48
394: 00e78023 sb a4,0(a5)
398: fe842783 lw a5,-24(s0)
39c: fff78793 addi a5,a5,-1
3a0: fef42423 sw a5,-24(s0)
3a4: fe842783 lw a5,-24(s0)
3a8: f007d8e3 bgez a5,2b8 <printInt+0xbc>
3ac: 00000013 nop
3b0: 05c12403 lw s0,92(sp)
3b4: 06010113 addi sp,sp,96
3b8: 00008067 ret
```
output with compiler Optimization
```
test: file format elf32-littleriscv
Disassembly of section .text:
00000100 <_start>:
100: 00000093 li ra,0
104: 00000113 li sp,0
108: 00000193 li gp,0
10c: 00000213 li tp,0
110: 00000293 li t0,0
114: 00000313 li t1,0
118: 00000393 li t2,0
11c: 00000413 li s0,0
120: 00000493 li s1,0
124: 00000513 li a0,0
128: 00000593 li a1,0
12c: 00000613 li a2,0
130: 00000693 li a3,0
134: 00000713 li a4,0
138: 00000793 li a5,0
13c: 00000813 li a6,0
140: 00000893 li a7,0
144: 00000913 li s2,0
148: 00000993 li s3,0
14c: 00000a13 li s4,0
150: 00000a93 li s5,0
154: 00000b13 li s6,0
158: 00000b93 li s7,0
15c: 00000c13 li s8,0
160: 00000c93 li s9,0
164: 00000d13 li s10,0
168: 00000d93 li s11,0
16c: 00000e13 li t3,0
170: 00000e93 li t4,0
174: 00000f13 li t5,0
178: 00000f93 li t6,0
0000017c <init_stack>:
17c: 00001117 auipc sp,0x1
180: 1d410113 addi sp,sp,468 # 1350 <__stack>
00000184 <SystemInit>:
184: 1a0000ef jal ra,324 <main>
188: 0040006f j 18c <SystemExit>
0000018c <SystemExit>:
18c: 00000073 ecall
00000190 <printInt>:
190: 32c00793 li a5,812
194: 0007ae03 lw t3,0(a5)
198: 0047a303 lw t1,4(a5)
19c: 0087a883 lw a7,8(a5)
1a0: 00c7a803 lw a6,12(a5)
1a4: 0107a583 lw a1,16(a5)
1a8: 0147a603 lw a2,20(a5)
1ac: 0187a683 lw a3,24(a5)
1b0: 01c7a703 lw a4,28(a5)
1b4: 0207a783 lw a5,32(a5)
1b8: fd010113 addi sp,sp,-48
1bc: 01c12623 sw t3,12(sp)
1c0: 00612823 sw t1,16(sp)
1c4: 01112a23 sw a7,20(sp)
1c8: 01012c23 sw a6,24(sp)
1cc: 00b12e23 sw a1,28(sp)
1d0: 02c12023 sw a2,32(sp)
1d4: 02d12223 sw a3,36(sp)
1d8: 02e12423 sw a4,40(sp)
1dc: 02f12623 sw a5,44(sp)
1e0: 00055a63 bgez a0,1f4 <printInt+0x64>
1e4: 400027b7 lui a5,0x40002
1e8: 02d00713 li a4,45
1ec: 00e78023 sb a4,0(a5) # 40002000 <__stack+0x40000cb0>
1f0: 40a00533 neg a0,a0
1f4: 35a4f7b7 lui a5,0x35a4f
1f8: 00c10593 addi a1,sp,12
1fc: fe810313 addi t1,sp,-24
200: 00000813 li a6,0
204: 90078693 addi a3,a5,-1792 # 35a4e900 <__stack+0x35a4d5b0>
208: fff00e93 li t4,-1
20c: 40002e37 lui t3,0x40002
210: 03000f13 li t5,48
214: 10d54263 blt a0,a3,318 <printInt+0x188>
218: 40d50533 sub a0,a0,a3
21c: 03900613 li a2,57
220: 00900893 li a7,9
224: 00100813 li a6,1
228: 0205a703 lw a4,32(a1)
22c: 40e687b3 sub a5,a3,a4
230: 00f54a63 blt a0,a5,244 <printInt+0xb4>
234: 40f50533 sub a0,a0,a5
238: 03800613 li a2,56
23c: 00800893 li a7,8
240: 00100813 li a6,1
244: 40e787b3 sub a5,a5,a4
248: 00f54a63 blt a0,a5,25c <printInt+0xcc>
24c: 40f50533 sub a0,a0,a5
250: 03700613 li a2,55
254: 00700893 li a7,7
258: 00100813 li a6,1
25c: 40e787b3 sub a5,a5,a4
260: 00f54a63 blt a0,a5,274 <printInt+0xe4>
264: 40f50533 sub a0,a0,a5
268: 03600613 li a2,54
26c: 00600893 li a7,6
270: 00100813 li a6,1
274: 40e787b3 sub a5,a5,a4
278: 00f54a63 blt a0,a5,28c <printInt+0xfc>
27c: 40f50533 sub a0,a0,a5
280: 03500613 li a2,53
284: 00500893 li a7,5
288: 00100813 li a6,1
28c: 40e787b3 sub a5,a5,a4
290: 00f54a63 blt a0,a5,2a4 <printInt+0x114>
294: 40f50533 sub a0,a0,a5
298: 03400613 li a2,52
29c: 00400893 li a7,4
2a0: 00100813 li a6,1
2a4: 40e787b3 sub a5,a5,a4
2a8: 00f54a63 blt a0,a5,2bc <printInt+0x12c>
2ac: 40f50533 sub a0,a0,a5
2b0: 03300613 li a2,51
2b4: 00300893 li a7,3
2b8: 00100813 li a6,1
2bc: 01c5a683 lw a3,28(a1)
2c0: 40e787b3 sub a5,a5,a4
2c4: 40e78733 sub a4,a5,a4
2c8: 40d706b3 sub a3,a4,a3
2cc: 02f54c63 blt a0,a5,304 <printInt+0x174>
2d0: 40f50533 sub a0,a0,a5
2d4: 02e55063 bge a0,a4,2f4 <printInt+0x164>
2d8: 03200613 li a2,50
2dc: 00100813 li a6,1
2e0: 00ce0023 sb a2,0(t3) # 40002000 <__stack+0x40000cb0>
2e4: ffc58593 addi a1,a1,-4
2e8: f2b316e3 bne t1,a1,214 <printInt+0x84>
2ec: 03010113 addi sp,sp,48
2f0: 00008067 ret
2f4: 40e50533 sub a0,a0,a4
2f8: 03100613 li a2,49
2fc: 00100813 li a6,1
300: fe1ff06f j 2e0 <printInt+0x150>
304: fee558e3 bge a0,a4,2f4 <printInt+0x164>
308: fdd89ce3 bne a7,t4,2e0 <printInt+0x150>
30c: fc080ce3 beqz a6,2e4 <printInt+0x154>
310: 01ee0023 sb t5,0(t3)
314: fd1ff06f j 2e4 <printInt+0x154>
318: 02f00613 li a2,47
31c: fff00893 li a7,-1
320: f09ff06f j 228 <printInt+0x98>
00000324 <main>:
324: 03700513 li a0,55
328: e69ff06f j 190 <printInt>
```
Observe the c code line 4 and 5.
``` =4
for(i=1;i<=N;i=i+1)
sum = sum +i;
```
Compile program with optimization will reduce some extra instruction.
If we know the value of N in advance, we can calculate the value of sum before program is executed.
| | Compile with -O3| Compile without optimization |
| -------- | -------- | -------- |
| total instruction | 321 | 2003 |
|Jump |101|293|
|Jump forwards|73|191|
|Jump backwards|28|102|
|Branch True|88|203|
|Branch False|19|87|
Compile with speed optimization, we can reduce a lot of jump instrcution.
And it can also reduce control hazard. If control hazard happens,it will result in wasting two cycle.
**readelf**
```
$ riscv-none-embed-readelf -h test
```
output
```
ELF Header:
Magic: 7f 45 4c 46 01 01 01 00 00 00 00 00 00 00 00 00
Class: ELF32
Data: 2's complement, little endian
Version: 1 (current)
OS/ABI: UNIX - System V
ABI Version: 0
Type: EXEC (Executable file)
Machine: RISC-V
Version: 0x1
Entry point address: 0x100
Start of program headers: 52 (bytes into file)
Start of section headers: 1464 (bytes into file)
Flags: 0x0
Size of this header: 52 (bytes)
Size of program headers: 32 (bytes)
Number of program headers: 1
Size of section headers: 40 (bytes)
Number of section headers: 9
Section header string table index: 8
```
The entry point address is the first instruction of this program.
The address is defined in linker script.
```
MEMORY {
mem : ORIGIN = 0x00000000, LENGTH = 0x00000100
imem : ORIGIN = 0x00000100, LENGTH = 0x00010000
}
/* Specify the default entry point to the program */
ENTRY(_start)
```
**size**
```
$ riscv-none-embed-size test
```
output
```
text data bss dec hex filename
160 0 4096 4256 10a0 test
```
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