## Note on Nov 3
Wait for the attendance until ==09:15==
* quiz4 on Nov 17: CPU datapath, control, pipeline.
single core processor
balance between power consumption and CPU frequency. CPU frequency is no longer the major factor for speed.
2 Control and Status Registers (CSRs) 7
2.1 CSR Address Mapping Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 CSR Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 CSR Field Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
vital for implementing supervisor programs such as OS kernel and hypervisors.
Verilog, SystemC, HDL
* separate the cross
* figure out and isotate the slowest component
folded reuse => implement multi-function circuit with MUX
instruction scheduling is a compiler optimization used to improve instruction-level parallelism, which improves performance on machines with instruction pipelines. Put more simply, it tries to do the following without changing the meaning of the code:
- Avoid pipeline stalls by rearranging the order of instructions.
- Avoid illegal or semantically ambiguous operations (typically involving subtle instruction pipeline timing issues or non-interlocked resources).
The pipeline stalls can be caused by structural hazards (processor resource limit), data hazards (output of one instruction needed by another instruction) and control hazards (branching).
> A memory barrier, also known as a membar, memory fence or fence instruction, is a type of barrier instruction that causes a central processing unit (CPU) or compiler to enforce an ordering constraint on memory operations issued before and after the barrier instruction. This typically means that operations issued prior to the barrier are guaranteed to be performed before operations issued after the barrier. => https://en.wikipedia.org/wiki/Memory_barrier
> downside: https://meltdownattack.com/
> Why is it called Spectre? The name is based on the root cause, speculative execution. As it is not easy to fix, it will haunt us for quite some time.
> information for speculative execution
> hints to optimizing compilers. e.g. https://stackoverflow.com/questions/109710/how-do-the-likely-unlikely-macros-in-the-linux-kernel-work-and-what-is-their-ben
## Note on Oct 13
- Next week: digital logic
+- as, ld, objdump, size,
riscv-none-embed-gcc : cross-compiler
| | |
| | product_name
option "-o" : output file name, ELF
volatile char* tx = (volatile char*) 0x40002000; /* address for UART */
MMIO (Memory mapping I/O)
recursive programs: depth / stack
code size reduction
* [Compiler Code Size Density](https://riscv.org/wp-content/uploads/2019/12/12.10-13.20c-Headline-Sponsor-Western-Digital-presents-GCC-Compiler-Code-Size-Density.pdf)
- WD is contributing to RISC-V ecosystem: https://www.westerndigital.com/company/innovations/risc-v
* [A deeply embedded processor for smart devices](https://ieeexplore.ieee.org/document/7046671)
FPGA -> implement your own GPU: https://www.slideshare.net/aj0612/sitcon2015
benefit: power consumption
deterministically / predictable
linker: relocate symbols
Format / extension:
vector extension as example: https://www.sifive.com/blog/risc-v-vector-extension-intrinsic-support
PC = PC + (immediate*4)
useful to implement switch-case
Arm (32-bits) has Thumb instructions (16-bits) => to improve Code Density
RISC-V (32-bit RV32) has compressed instructions (16-bits) => to improve Code Density
> violation of fixed length encoding (exceptional), RV32"C"
RISC machine/core (concepts)
CSR: control registers: https://opencores.org/projects/potato/control%20registers
> RISC-V Privileged ISA